Features: • 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
• Supports serial bus data rates of 100, 200, and 400 Mbits/s
• Provides bus-hold buffers on physical interface for low-cost single capacitor isolation
• Supports physical write posting of up to three outstanding transactions
• Serial ROM interface supports 2-wire devices
• Supports external cycle timer control for customized synchronization
• Implements PCI burst transfers and deep FIFOs to tolerate large host latency
• Provides two general-purpose I/Os
• Fabricated in advanced low-power CMOS process
• Packaged in 100 LQFP (PZ)
• Supports CLKRUN
• Drop-in replacement for the TSB12LV22
• Supports PCI and CardBus applicationsPinout
SpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V
Supply voltage range, VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V
Input voltage range for PCI, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 to VCCP + 0.5 V
Input voltage range for Miscellaneous and PHY interface, VI . . . . . . . . 0.5 to VCCI + 0.5 V
Output voltage range for PCI, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 to VCCP + 0.5 V
Input voltage range for Miscellaneous and PHY interface, VO . . . . . . . . 0.5 to VCCP + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . .±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . ±20 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
NOTES:
1. Applies to external input and bidirectional buffers. For 5-V tolerant use VI > VCCI. For PCI use VI > VCCP.
2. Applies to external output and bidirectional buffers. For 5-V tolerant use VO > VCCI. For PCI use VO > VCCP.
DescriptionThe Texas Instruments TSB12LV23 is a PCI-to-1394 host controller compatible with the latest PCI Local Bus, PCI
Bus Power Management Interface, IEEE 1394-1995, and 1394 Open Host Controller Interface Specifications. The
chip provides the IEEE 1394 link function, and is compatible with serial bus data rates of 100 Mbits/s, 200 Mbits/s,
and 400 Mbits/s.
As required by the 1394 Open Host Controller Interface (OHCI) and IEEE 1394A Specifications, internal control
registers are memory mapped and non-prefetchable. The PCI configuration header is accessed through
configuration cycles specified by PCI, and provides Plug-and-Play (PnP) compatibility. Furthermore, the TSB12LV23
is compliant with the PCI Bus Power Management Interface Specification, per the PC 98 requirements. TSB12LV23
supports the D0, D2, and D3 power states.
The TSB12LV23 design provides PCI bus master bursting, and is capable of transferring a cacheline of data at 132
Mbytes/s after connection to the memory controller. Since PCI latency can be large even on a PCI Revision 2.1
system, deep FIFOs are provided to buffer 1394 data.
The TSB12LV23 provides physical write posting buffers and a highly tuned physical data path for SBP-2 performance.
The TSB12LV23 also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal
arbitration, and bus holding buffers on the PHY/Link interface, thus, making the TSB12LV23 the best-in-class 1394
OHCI solution.
An advanced CMOS process is used to achieve low power consumption while operating at PCI clock rates up to
33 MHz.
TSB12LV23 Data Sheet
