Features: · Designed to 1394 Open Host Controller Interface (OHCI) Specification
· IEEE 1394-1995 Compliant and Compatible with Proposal 1394A
· Compliant to Latest PCI Specification, PCI 2.2
· PCI Power Management Compliant
· 3.3-V Core Logic with Universal PCI Interface Compatible with 3.3-V and 5-V PCI Signaling Environments
· Supports Serial Bus Data Rates of 100, 200, and 400 Mbits/s
· Provides Bus-Hold Buffers on Physical I/F for Low-Cost Single Capacitor Isolation
· Supports Physical Write Posting of Up to Three Outstanding Transactions
· Serial ROM Interface Supports 2-Wire Devices
· Supports External Cycle Timer Control for Customized Synchronization
· Implements PCI Burst Transfers and Deep FIFOs to Tolerate Large Host Latency
· Provides up to Four General Purpose I/Os
· Fabricated in Advanced Low-Power CMOS Process
· Packaged in 100 LQFP (PZP)
Pinout
SpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 3.6 V
Supply voltage range, VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 5.5 V
Supply voltage range, VCCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V
Input voltage range for PCI, VI . . . . . . . . . . . . . . . . . . . . . . . .0.5 to VCCP + 0.5 V
Input voltage range for Miscellaneous and Phy I/F, VI . . . . . . .0.5 to VCCI + 0.5 V
Output voltage range for PCI, VO . . . . . . . . . . . . . . . . . . . . . 0.5 to VCCP + 0.5 V
Input voltage range for Miscellaneous and Phy I/F, VO . . . . . 0.5 to VCCP + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . .±20 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C
NOTES:
1. Applies to external input and bidirectional buffers. For 5-V tolerant use VI > VCCI. For PCI use VI > VCCP.
2. Applies to external output and bidirectional buffers. For 5-V tolerant use VO > VCCI. For PCI use VO > VCCP.DescriptionThe Texas Instruments OHCI-LynxE is a PCI-to-1394 host controller compatible with the latest PCI, IEEE1394, and 1394 OHCI 1.00 specifications. The chip provides the IEEE1394 link function, and is compatible with serial bus data rates of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.
As required by the 1394 OHCI Specification, internal control registers are memory mapped and non-prefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI, and provides Plug-and-Play (PnP) compatibility. Furthermore, the OHCI-Lynx is compliant with the PCI Power Management Specification, per the PC 498 requirements.
The OHCI-Lynx design provides PCI bus master bursting, and is capable of transferring a cacheline of data at 132 Mbytes/s after connection to the memory controller. Since PCI latency can be large even on a PCI Revision 2.1 system, deep FIFOs are provided to buffer 1394 data.
Physical write posting buffers are provided to enhance serial bus performance, and multiple isochronous channels are provided for simultaneous operation of real-time applications. The OHCI-Lynx also provides bus holding buffers on the phy interface for simple and cost effective single capacitor isolation. An advanced CMOS process is used to achieve low power consumption while operating at PCI clock rates up to 33 MHz.
TSB12LV22 Data Sheet
