TSB12C01A

Link
• Complies With IEEE-1394-1995 Standard
• Transmits and Receives Correctly Formatted 1394 Packets
• Supports Isochronous Data Transfer
• Performs Function of Cycle Master
• Generates and Checks 32-Bit CRC
• Detects Lost Cycle-Start Messages
• Contains Asynchronous, Isochronous, and General-Receive FIFOs
Physical-Link Interface
• Interfaces Directly to the TSB11C01, TSB11LV01, TSB14C01, and TSB21LV03 Phy Chips
• Supports Speeds of 100, 200, and 400 Mb/s
• Implements the Physical-Link Interface Described in Annex J of the IEEE 1394-1995 Standard
• Supports TI Bus Holder Isolation External Implementation
Host Bus Interface
• Provides Chip Control With Directly Addressable Registers
• Is Interrupt Driven to Minimize Host Polling
• Has a Generic 32-Bit Host Bus Interface
General
• Requires a Single 5-V ±5% Power Supply
• Manufactured with Low-Power CMOS Technology
• Packaged in a 100-Pin Thin Quad Flat Package (TQFP) (PZ Package) for 0°C to 70°C and 40°C to 85°C Operation
• Packaged in a 100-Pin Ceramic Quad Flat Package (WN Package) for 55°C to 125°C Operation

Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 6 V
Input voltage range, at any input, VI . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 2) . . . . . . . . . . . . . ±20 mA
Continuous total power dissipation . . . . . . . See Maximum Dissipation Rating Table
Output clamp current, IOK (VO < 0 or VO > V_CC) (see Note 3) . . . . . . . . .. ±20 mA
Operating free-air temperature range, TA: A suffix . . . . . . . . . . . . . . 0°C to 70°C
Operating free-air temperature range, TA: AI suffix . . . . . . . . . . . 40°C to 85°C
Operating free-air temperature range, TA: AM suffix . . . . . . . . .  55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Case temperature for 10 seconds, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  260°C
NOTES:
1. All voltage values are with respect to GND.
2. This applies to all inputs.
3. This applies to all outputs.

The TSB12C01A is an IEEE 1394-1995 standard (from now on referred to only as 1394) high-speed serial-bus link-layer controller that allows for easy integration into an I/O subsystem. The TSB12C01A transmits and receives correctly formatted 1394 packets and generates and inspects the 32-bit cyclic redundancy check (CRC). The TSB12C01A is capable of being a cycle master and supports reception of isochronous data on two channels. It interfaces directly to the TSB11C01, TSB11LV01, and TSB21LV03 physical-layer chips and can support bus speeds of 100, 200, and 400 Mb/s. The TSB12C01A has a generic 32-bit host bus interface, which makes connection to most 32-bit host buses very simple. The TSB12C01A has software-adjustable FIFOs for optimal FIFO size and performance characterization and allows for variable-size asynchronous-transmit FIFO (ATF), isochronous-transmit FIFO (ITF), and general-receive FIFO (GRF).

This document is not intended to serve as a tutorial on 1394; users should refer to the IEEE 1394-1995 serial bus for detailed information regarding the 1394 high-speed serial bus.