Features: • Single-chip CDR circuit for 622 Mb/s data• Exceeds Bellcore and ITU jitter tolerance maps• Single-ended ECL input has loopthrough path for external 50 ohm termination to minimize stubs and reflections• Clock and data outputs are differential ECL• Provides ...
TQ8103: Features: • Single-chip CDR circuit for 622 Mb/s data• Exceeds Bellcore and ITU jitter tolerance maps• Single-ended ECL input has loopthrough path for external 50 ohm termination t...
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Parameter | Symbol | Minimum | Nominal | Maximum | Unit |
Positive supply | VCC | 0 | 7 | V | |
Negative supply | VEE | -7 | 0 | V | |
Output voltage | VO | ECL | VEE 0.5 | +0.5 | V |
Output current | IO | ECL | - | 40 | mA |
Input voltage | VI | ECL | VEE 0.5 | +0.5 | V |
Input current | II | ECL | -1 | 1 | mA |
Input current | VO | TTL | -0.5 | VCC + 0.5 | V |
Output current | IO | TTL | 20 | mA | |
Input voltage | VI | TTL | 0.5 | VCC + 0.5 | V |
Input current | II | TTL | -1 | 1 | mA |
Junction temperature | TJ | -55 | +150 | ° C | |
Storage temperature | TS | -65 | +175 | ° C | |
Power dissipation | PD | 2 | W |
The TQ8103 is a monolithic clock and data recovery (CDR) IC that receives NRZ data, extracts the high-speed clock, and presents the separated data and clock as its outputs. This device is designed specifically for SONET OC-12 and SDH STM-4 applications at 622 Mb/s.
TQ8103's on-chip phase-locked loop (PLL) generates a stable 622.08 Mb/s reference based upon an external 38.88 MHz TTL reference. The PLL is based on a VCO constructed from integrated reactive components, which form a low-jitter, high-Q differential tank circuit. Both frequency- and phase-detect circuits reliably acquire and hold lock in worst-case SONET jitter conditions and scrambling patterns. The lock-detect circuitry of TQ8103 signals when the CDR acquires frequency lock.