Features: • >20 Gb/s aggregate BW• 1.25 Gb/s/port NRZ data rate• Non-blocking architecture• 500 ps delay match• Differential PECL-level data I/O; Selectable CMOS/TTLlevel control inputs• Low jitter and signal skew• Fully differential data path• Do...
TQ8017: Features: • >20 Gb/s aggregate BW• 1.25 Gb/s/port NRZ data rate• Non-blocking architecture• 500 ps delay match• Differential PECL-level data I/O; Selectable CMOS/TTL...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Symbol |
Parameter |
Absolute Max. Rating |
Notes |
TSTOR |
Storage Temperature |
65° C to +150° C |
|
TCH |
Junction (Channel) Temperature |
65° C to +150° C |
1 |
TC |
Case Temperature Under Bias |
65° C to +125° C |
2 |
VCC |
Supply Voltage |
0 V to +7 V |
3 |
VTT |
Load Termination Supply Voltage |
VCC to 0 V |
4 |
VIN |
Voltage Applied to Any PECL Input; Continuous |
GND 0.5 V to VCC +0.5 V |
|
IIN |
Current Into Any PECL Input; Continuous |
1.0 mA to +1.0 mA |
|
VIN |
Voltage Applied to Any TTL/CMOS Input; Continuous |
0.5 V to VCC +0.5 V |
|
IIN |
Current Into Any TTL/CMOS Input; Continuous |
1.0 mA to +1.0 mA |
|
VOUT |
Voltage Applied to Any PECL Output |
GND 0.5 V to VCC +0.5 V |
4 |
IOUT |
Current From Any PECL Output; Continuous |
40 mA |
|
PD |
Power Dissipation per Output POUT = (GND VOUT) x IOUT |
50 mW |
The TQ8017 is a non-blocking 16 x 16 digital crosspoint switch capable of data rates greater than 1.25 Gigabits per second per port. Utilizing a fully differential internal data path and PECL I/O, the TQ8017 offers a high data rate with exceptional signal fidelity. The symmetrical switching and noise rejection characteristics inherent in differential logic result in low jitter and signal skew. The TQ8017 is ideally suited for digital video, data communications and telecommunication switching applications.
The non-blocking architecture of TQ8017 uses 16 fully independent 16:1 multiplexers (see diagram on page 2), allowing each output port to be independently programmed to any input port. The switch is configured by sequentially loading each multiplexer's 4-bit program latch (OA0:3) with the desired input port address (IA0:3) and enabling the LOAD pin. When complete, the CONFIGURE pin of TQ8017 is strobed and all new configurations are simultaneously transferred into the switch multiplexers. Data integrity is maintained on all unchanged data paths.