Features: • >1.3 Gigabit/sec data rate• Non-blocking architecture• +200 ps delay match (one input to all outputs)• ECL-level data inputs/outputs; CMOS-level control inputs• Low crosstalk• Fully differential data path• Double row of output select latches...
TQ8016: Features: • >1.3 Gigabit/sec data rate• Non-blocking architecture• +200 ps delay match (one input to all outputs)• ECL-level data inputs/outputs; CMOS-level control inputs...
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Symbol |
Parameter |
Absolute Max. Rating |
Notes |
TSTOR |
Storage Temperature |
65° C to +150° C |
|
TJ |
Junction Temperature |
65° C to +150° C |
1 |
TC |
Case Temperature Under Bias |
65° C to +125° C |
2 |
VCC |
Supply Voltage |
0 V to +7 V |
2 |
VEE |
Supply Voltage |
7 V to 0 V |
3 |
VTT |
Load Termination Supply Voltage |
VEE to 0 V |
|
VIN |
Voltage Applied to Any ECL Input; Continuous |
VEE 0.5 V to +0.5 V |
|
IIN |
Current Into Any ECL Input; Continuous |
1.0 mA to +1.0 mA |
|
VIN |
Voltage Applied to Any TTL/CMOS Input; Continuous |
0.5 V to VCC +0.5 V |
|
IIN |
Current Into Any TTL/CMOS Input; Continuous |
1.0 mA to +1.0 mA |
|
VOUT |
Voltage Applied to Any ECL Output |
VEE 0.5 V to +0.5 V |
3 |
IOUT |
Current From Any ECL Output; Continuous |
40 mA |
|
PD |
Power Dissipation per Output POUT = (GND VOUT) x IOUT |
50 mW |
The TQ8016 is a 16 x 16 differential digital crosspoint switch capable of handling 1.3 Gbit/s data rate. The high data rate and exceptional signal fidelity is made possible with TriQuint's fully differential Source-Coupled FET Logic (SCFL) standard cells. The symmetrical switching characteristic inherent in differential logic results in low signal skew and crosstalk for maximum signal fidelity.
The user can independently configure any switch output to any input, including an input chosen by another output. To configure the switch, the 4-bit output address (OA0..3) is decoded to enable the loading of the 4-bit input selection data (IA0..3) on the rising edge of the LOAD signal. The process of TQ8016 is repeated until all desired connections are programmed. By bringing the CONFIGURE signal high, the contents of the Output Select Latches are transferred in parallel to a second row of 4-bit latches (R2), causing the switch reconfiguration.
This double row architecture of TQ8016 minimizes the time to completely reconfigure the switch since a new set of addresses can be loaded to the Output Select Latches (R1) while the switch is active (transmitting). At the time of reconfiguration, no data drop-out occurs for any output whose input connection does not change.
For applications which do not require synchronous configuration of the switch, the LOAD and CONFIGURE inputs of TQ8016 may be tied together.