Features: `High-Performance Static CMOS Technology
`TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
24-MHz System Clock (60-MHz Pipeline)
Independent 16/32-Bit Instruction Set
Open Architecture With Third-Party Support
Built-In Debug Module
Utilizes Big-Endian Format
`Integrated Memory
512K-Byte Program Flash
Two Banks With 14 Contiguous Sectors
Internal State Machine for Program and Erase
32K-Byte Static RAM (SRAM)
`Operating Features
Core Supply Voltage (VCC): 1.81 V - 2.05 V
I/O Supply Voltage (VCCIO): 3.0 V - 3.6 V
Low-Power Modes: STANDBY and HALT
Industrial and Automotive Temperature Ranges
`470+ System Module
32-Bit Address Space Decoding
Bus Supervision for Memory and Peripherals
Analog Watchdog (AWD) Timer
Real-Time Interrupt (RTI)
System Integrity and Failure Detection
`Direct Memory Access (DMA) Controller
32 Control Packets and 16 Channels
`Frequency-Modulated Phase-Locked Loop (FMPLL)-Based Clock Module With Prescaler
Multiply-by-4 or -8 Internal FMPLL Option
`Seven Communication Interfaces:
Two Serial Peripheral Interfaces (SPIs)
255 Programmable Baud Rates
Serial Communications Interfaces (SCI)
224 Selectable Baud Rates
Asynchronous/Isosynchronous Modes
Two High-End CAN Controllers:
32-Mailbox Capacity
Fully Compliant With CAN Protocol, Version 2.0B
Multi-Buffered Serial Peripheral Interface (MibSPI)
128-Word Buffer
Four DMA Channels
Six Chip Selects
Class II Serial Interface (C2SIb)
Two Selectable Data Rates
Normal Mode 10.4 Kbps and 4X Mode 41.6 Kbps
`High-End Timer (HET)
32 Programmable I/O Channels:
30 High-Resolution Pins
2 Standard-Resolution Pins
High-Resolution Share Feature (XOR)
High-End Timer RAM
128-Instruction Capacity
`Two 10-Bit, 16-Channel Multi-Buffered ADCs
128-Word FIFO Buffer
Single- or Continuous-Conversion Modes
1.55 s Minimum Sample and Conversion Time
Calibration Mode and Self-Test Features
`Four External Interrupts
`Flexible Interrupt Handling
`3 Dedicated General-Purpose I/O (GIO) Pins, 1 Input-Only GIO Pin, and 65 Additional Peripheral I/Os
`Compatible ROM Device (Planned)
`On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1† (JTAG) Test-Access Port
`176-Pin Plastic Ball Grid Array (GJZ Suffix)
`Development System Support Tools Available
Code Composer Studio™ Integrated Development Environment (IDE)
HET Assembler and Simulator
Real-Time In-Circuit Emulation
Flash Programming
`External Clock Prescale (ECP) Module
Programmable Low-Frequency External Clock (CLK)SpecificationsSupply voltage ranges: VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V
Supply voltage ranges: VCCIO, VCCAD, VCCP (flash pump) (see Note 1) . . . . . . . . −0.5 V to 4.1 V
Input voltage range: All input pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . −0.5 V to 4.1 V
Input clamp current: IIK (VI < 0 or VI > VCCIO)
All pins except ADIN[0:11], PORRST, TRST, TEST and TCK . . .. . . . . . . . . . . . . . . . . . . . . . ±20 mA
IIK (VI < 0 or VI > VCCAD)
ADIN[0:11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Operating free-air temperature ranges, TA: A version . . . . . . . . . . . . . . . . . . . . . . . −40 to 85
T version . . . . . . . . . . . . . .. . . .. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 to 105
Q version . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. ... −40 to 125
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . .. . . .. . . .. . . . . . −40 to 150
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to 150
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to their associated grounds.
DescriptionThe TMS470R1VF67A† device is a member of the Texas Instruments TMS470R1x family of general-purpose 16/32-bit reduced instruction set computer (RISC) microcontrollers. The VF67A microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The TMS470R1VF67A utilizes the big-endian format where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte.
High-end embedded control applications demand more performance from their controllers while maintaining low costs. The VF67A RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption.
The TMS470R1VF67A device contains the following:
·ARM7TDMI 16/32-Bit RISC CPU
·TMS470R1x system module (SYS) with 470+ enhancements [including a 16-channel direct-memory access (DMA) controller
·512K-byte flash
·32K-byte SRAM
·Frequency-modulated phase-locked loop (FMPLL) clock module
·Analog watchdog (AWD) timer
·Real-time interrupt (RTI) module
·Two serial peripheral interface (SPI) modules
·One serial communications interface (SCI) module
·Two high-end CAN controllers (HECC)
·Class II serial interface (C2SIb)
·Two 10-bit multi-buffered analog-to-digital converters (MibADC), 16-input channels
·Multi-buffered serial peripheral interface (MibSPI) module
·High-end timer (HET) controlling 32 I/Os
·External Clock Prescale (ECP) module
·Up to 68 I/O pins and 1 input-only pin
The functions performed by the 470+ system module (SYS) include: address decoding; memory protection; memory and peripherals bus supervision; reset and abort exception management; prioritization for all internal interrupt sources; device clock control; and parallel signature analysis (PSA). This data sheet includes devicespecific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189).
The TMS470R1VF67A memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes.
The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface.The flash operates with a system clock frequency of up to 24 MHz. When in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz. For more detailed information on the flash, see the flash section of this data sheet and the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).
TMS470R1VF67A Data Sheet
