Features: ` High-Performance Static CMOS Technology
` TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
24-MHz System Clock (60-MHz Pipeline Mode)
Independent 16/32-Bit Instruction Set
Open Architecture With Third-Party Support
Built-In Debug Module
Utilizes Big-Endian Format
` Integrated Memory
512K-Byte Program Flash
` 2 Banks With 14 Contiguous Sectors
` Internal State Machine for Programmingand Erase
32K-Byte Static RAM (SRAM)
` 27 Dedicated GIO Pins, 1 Input-Only GIO Pin, and 59 Additional Peripheral I/Os
` Operating Features
Core Supply Voltage (V CC ): 1.81 V 2.05
I/O Supply Voltage (VCCIO): 3.0 V 3.6 V
Low-Power Modes: STANDBY and HALT
Extended Industrial Temperature Range
` 470+ System Module
32-Bit Address Space Decoding
Bus Supervision for Memory and Peripherals
Analog Watchdog (AWD) Timer
Real-Time Interrupt (RTI)
System Integrity and Failure Detection
Interrupt Expansion Module (IEM)
` Direct Memory Access (DMA) Controller
32 Control Packets and 16 Channels
` Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock Module With Prescaler
Multiply-by-4 or -8 Internal ZPLL Option
ZPLL Bypass Mode
` External Clock Prescale (ECP) Module
Programmable Low-Frequency Externa Clock (CLK)
` Seven Communication Interfaces:
Three Serial Peripheral Interfaces (SPIs)
` 255 Programmable Baud Rates
Two Serial Communications Interfaces (SCIs)
` 224 Selectable Baud Rates
` Asynchronous/Isosynchronous Modes
` Two High-End CAN Controllers (HECCs)
` 32-Mailbox Capacity Each
` Fully Compliant With CAN Protocol, Version 2.0B
` High-End Timer (HET)
32 Programmable I/O Channels:
` 24 High-Resolution Pins
` 8 Standard-Resolution Pins
High-Resolution Share Feature (XOR)
High-End Timer RAM
` 128-Instruction Capacity
` 16-Channel 10-Bit Multi-Buffered ADC (MibADC)
128-Word FIFO Buffer
Single- or Continuous-Conversion Modes
1.55 ms Minimum Sample and Conversion Time
Calibration Mode and Self-Test Features
` Eight External Interrupts
` Flexible Interrupt Handling
` On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1(1) (JTAG) Test-Access Port
` 144-Pin Plastic Low-Profile Quad Flatpack (PGE Suffix)
1) The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. Boundary scan is not supported on this device.Pinout
Specificationsover operating free-air temperature range, T version (unless otherwise noted)(1)
Supply voltage range: VCC(2) ................................ -0.3 V to 2.5 V
Supply voltage range: VCCIO , VCCAD , VCCP (flash pump)(2) ..............-0.3 V to 4.1V
Input voltage range: All input pins ..............................-0.3 V to 4.1V
Input clamp current: IIK (VI < 0 or VI > VCCIO)
All pins except ADIN[0:11], PORRST, TRST , TEST, and TCK........±20 mA
IIK (VI < 0 or VI > VCCAD)
ADIN[0:15].................................... ±10 mA
Operating free-air temperature range, TA: T version ....................-40 to 105
Operating junction temperature ranges, TJ.......................... -40 to 150
Storage temperature range, Tstg ................................-65 to 150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to their associated grounds.
DescriptionThe TMS470R1B512(1) device is a member of the Texas Instruments (TI) TMS470R1x family of general- purpose16/32-bit reduced instruction set computer (RISC) microcontrollers. The B512 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The B512 utilizes the big-endian format, where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte.
High-end embedded control applications demand more performance from their controllers while maintaining low costs. The B512 RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption.
The B512 device contains the following:
· ARM7TDMI 16/32-Bit RISC CPU
· TMS470R1x system module (SYS) with 470+ enhancements [including an interrupt expansion module (IEM) and a 16-channel direct-memory access (DMA) controller]
· 512K-byte flash
· 32K-byte SRAM
· Zero-pin phase-locked loop (ZPLL) clock module
· Analog watchdog (AWD) timer
· Real-time interrupt ( RTI) module
· Three serial peripheral interface (SPI) modules
· Two serial communications interface (SCI) modules
· Two high-end CAN controller (HECC) modules
· 10-bit multi-buffered analog-to-digital converter (MibADC) with 16 input channels
· High-end timer (HET) controlling 32 I/Os
· External clock prescale (ECP) module
· Up to 86 I/O pins and 1 input-only pin
The functions performed by the 470+ system module (SYS) include:
· Address decoding
· Memory protection
· Memory and peripherals bus supervision
· Reset and abort exception management
· Expanded interrupt capability with prioritization for all internal interrupt sources
· Device clock control
· Direct-memory access (DMA) and control
· Parallel signature analysis (PSA).
This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189). For a more detailed functional description of the IEM module, see the TMS470R1x Interrupt Expansion Module (IEM) Reference Guide (literature number SPNU211). For a more detailed functional description of the DMA module, see the TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194).
The B512 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes.
(1) The TMS470R1B512 device name will be referred to as either the full device name or as B512 throughout the remainder of this document.
TMS470R1B512 Data Sheet
