TMS470R1B1M Selling Leads, Price trend, TMS470R1B1M DataSheet download, circuit diagram from SeekIC.com

Features: ` High-Performance Static CMOS Technology ` 32-Mailbox Capacity` TMS470R1x 16/32-Bit RISC Core ` Fully Compliant With CAN Protocol, (ARM7TDMI™) Version 2.0B 60-MHz System Clock (Pipeline Mode) Five Inter-Integrated Circuit (I2C) Modules Independent 16/32-Bit Instruction Set ` M...

Product Details

Description

Features:

` High-Performance Static CMOS Technology
` 32-Mailbox Capacity
` TMS470R1x 16/32-Bit RISC Core
` Fully Compliant With CAN Protocol, (ARM7TDMI™) Version 2.0B
    60-MHz System Clock (Pipeline Mode)
    Five Inter-Integrated Circuit (I2C) Modules
    Independent 16/32-Bit Instruction Set
` Multi-Master and Slave Interfaces
    Open Architecture With Third-Party Support
` Up to 400 Kbps (Fast Mode)
    Built-In Debug Module
` 7- and 10-Bit Address Capability
` Integrated Memory
` High-End Timer Lite (HET)
    1M-Byte Program Flash
    12 Programmable I/O Channels:
` Two Banks With 16 Contiguous Sectors
` 12 High-Resolution Pins
    64K-Byte Static RAM (SRAM)
    High-Resolution Share Feature (XOR)
    Memory Security Module (MSM)
     High-End Timer RAM
    JTAG Security Module
` 64-Instruction Capacity
` Operating Features
` External Clock Prescale (ECP) Module
    Low-Power Modes: STANDBY and HALT
    Programmable Low-Frequency External
    Industrial Temperature Range Clock (CLK)
` 470+ System Module
` 12-Channel, 10-Bit Multi-Buffered ADC
    32-Bit Address Space Decoding (MibADC)
    Bus Supervision for Memory/Peripherals
    64-Word FIFO Buffer
    Digital Watchdog (DWD) Timer
    Single- or Continuous-Conversion Modes
    Analog Watchdog (AWD) Timer
    1.55 s Minimum Sample and Conversion Time
    Enhanced Real-Time Interrupt (RTI)
    Calibration Mode and Self-Test Features
    Interrupt Expansion Module (IEM)
` Flexible Interrupt Handling
    System Integrity and Failure Detection
` Expansion Bus Module (EBM)
    ICE Breaker
    Supports 8- and 16-Bit Expansion Bus
` Direct Memory Access (DMA) Controller Memory Interface Mappings
    32 Control Packets and 16 Channels
    42 I/O Expansion Bus Pins
` Zero-Pin Phase-Locked Loop (ZPLL)-Based
` 46 Dedicated General-Purpose I/O (GIO) Pins Clock Module With Prescaler and 47 Additional Peripheral I/Os
    Multiply-by-4 or -8 Internal ZPLL Option
` Sixteen External Interrupts
    ZPLL Bypass Mode
` On-Chip Scan-Base Emulation Logic, IEEE
` Twelve Communication Interfaces: Standard 1149.1(1) (JTAG) Test-Access Port
    Two Serial Peripheral Interfaces (SPIs)
` 144-Pin Plastic Low-Profile Quad Flatpack
    255 Programmable Baud Rates (PGE Suffix)
   Three Serial Communication Interfaces (1) The test-access port is compatible with the IEEE Standard
(SCIs) 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. Boundary scan is not
` 224 Selectable Baud Rates supported on this device.
` Asynchronous/Isosynchronous Modes

Pinout

Connection Diagram

Specifications

over operating free-air temperature range, A version (unless otherwise noted)⁽¹⁾
Supply voltage ranges: VCC⁽²⁾ ........................................................-0.3 V to 2.5 V
Supply voltage ranges: VCCIO, VCCAD, VCCP (flash pump)⁽²⁾ ........-0.3 V to 4.1 V
Input voltage range: All 5 V tolerant input pins ...............................-0.3 V to 6.0 V
All other input pins ...........................................................................-0.3 V to 4.1 V
Input clamp current: IIK (VI < 0 or VI > VCCIO)
All pins except ADIN[0:11], PORRST, TRST , TEST,and TCK .........................±20 mA
IIK (VI < 0 or VI > VCCAD)
ADIN[0:11]................................................................................................. ±10 mA
Operating free-air temperature A version ...........................................-40 to 85
ranges, TA:
Operating junction temperature range, TJ:..................................... -40°C to 150
Storage temperature range, Tstg:.................................................... -40 to 150

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to their associated grounds.

Description

The TMS470R1B1M(1) devices are members of the Texas Instruments TMS470R1x family of general-purpose 16/32-bit reduced instruction set computer (RISC) microcontrollers. The B1M microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The TMS470R1B1M utilizes the big-endian format where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte.

High-end embedded control applications demand more performance from their controllers while maintaining low costs. The B1M RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption.

The TMS470R1B1M devices contain the following:
· ARM7TDMI 16/32-Bit RISC CPU
· TMS470R1x system module (SYS) with 470+ enhancements
· 1M-byte flash
· 64K-byte SRAM
· Zero-pin phase-locked loop (ZPLL) clock module
· Digital watchdog (DWD) timer
· Analog watchdog (AWD) timer
· Enhanced real-time interrupt ( RTI) module
· Interrupt expansion module (IEM)
· Memory security module (MSM)
· JTAG security module
· Two serial peripheral interface (SPI) modules
· Three serial communications interface (SCI) modules
· Two high-end CAN controllers (HECC)
· Five inter-integrated circuit (I2C) modules
· 10-bit multi-buffered analog-to-digital converter (MibADC), with 12 input channels
· High-end timer lite (HET) controlling 12 I/Os
· External clock prescale (ECP)
· Expansion bus module (EBM)
· Up to 93 I/O pins
The functions performed by the 470+ system module (SYS) include:
· Address decoding
· Memory protection
· Memory and peripherals bus supervision
· Reset and abort exception management
· Prioritization for all internal interrupt sources
· Device clock control
· Parallel signature analysis (PSA)

The enhanced real-time interrupt (RTI) module on the B1M has the option to be driven by the oscillator clock. The digital watchdog (DWD) is a 25-bit resettable decrementing counter that provides a system reset when the watchdog counter expires. This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189).

TMS470R1B1M

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