Features: ` High-Performance Static CMOS Technology
` Asynchronous/Isosynchronous Modes
` TMS470R1x 16/32-Bit RISC Core
Standard CAN Controller (SCC) (ARM7TDMI™)
16-Mailbox Capacity
24-MHz System Clock (48-MHz Pipeline
` Fully Compliant With CAN Protocol, Version Mode) 2.0B
Independent 16/32-Bit Instruction Set
Class II Serial Interface (C2SIa)
Open Architecture With Third-Party Support
` Two Selectable Data Rates
Built-In Debug Module
` Normal Mode 10.4 Kbps and 4X Mode 41.6
Big-Endian Format Utilized Kbps
` Integrated Memory
` High-End Timer (HET)
64K-Byte Program Flash
13 Programmable I/O Channels:
` One Bank With Five Contiguous Sectors
` 12 High-Resolution Pins
` Internal State Machine for Programming
` 1 Standard-Resolution Pin and Erase
High-Resolution Share Feature (XOR)
4K-Byte Static RAM (SRAM)
HET RAM (64-Instruction Capacity)
` Operating Features
` 10-Bit Multi-Buffered ADC (MibADC)
Core Supply Voltage (VCC): 1.71 V2.05 V 8-Channel
I/O Supply Voltage (VCCIO): 3.0 V3.6 V
64-Word FIFO Buffer
Low-Power Modes: STANDBY and HALT
Single- or Continuous-Conversion Modes
Industrial Temperature Ranges
1.55 ms Minimum Sample and Conversion
` 470+ System Module Time
32-Bit Address Space Decoding
Calibration Mode and Self-Test Features
Bus Supervision for Memory and
` Six External Interrupts Peripherals
` Flexible Interrupt Handling
Analog Watchdog (AWD) Timer
` 5 Dedicated General-Purpose I/O (GIO) Pins, 1
Real-Time Interrupt (RTI) Input-Only GIO Pin, and 34 Additional
System Integrity and Failure Detection Peripheral I/Os
` Zero-Pin Phase-Locked Loop (ZPLL)-Based
` External Clock Prescale (ECP) Module Clock Module With Prescaler
Programmable Low-Frequency External
Multiply-by-4 or -8 Internal ZPLL Option Clock (CLK)
ZPLL Bypass Mode
` On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1 (1) (JTAG) Test-Access Port
` Six Communication Interfaces:
` 80-Pin Plastic Low-Profile Quad Flatpack (PN
Two Serial Peripheral Interfaces (SPIs) Suffix)
` 255 Programmable Baud Rates (1) The test-access port is compatible with the IEEE Standard
Two Serial Communication Interfaces (SCIs) 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. Boundary scan is not sup-
` 224 Selectable Baud Rates ported on this device.Pinout
SpecificationsSupply voltage ranges: VCC(2) ...........................................................-0.5 V to 2.5 V
Supply voltage ranges: VCCIO , VCCAD , VCCP (Flash pump)(2)......... -0.5 V to 4.1 V
Input voltage range: All input pins...................................................... -0.5 V to 4.1 V
Input clamp current: I IK (V I < 0 or V I > VCCIO )....................................... ± 20 mA
All pins except ADIN[0:11], PORRST, TRST , TEST and TCK
I IK (V I < 0 or V I > VCCAD ) .........................................................................±10 mA
ADIN[0:11]
Operating free-air temperature ranges, T A :......................................... -40 to 85
Operating junction temperature range, T J ............................................-40to 150
Storage temperature range, Tstg........................................................ -65 to 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to their associated grounds.DescriptionThe TMS470R1A64 (1) device is a member of the Texas Instruments TMS470R1x family of general-purpose16/32-bit reduced instruction set computer (RISC) microcontrollers. The A64 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining high code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection bytes numbered upwards from 0. The TMS470R1A64 utilizes the big-endian format, where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte.
High-end embedded control applications demand more performance from their controllers while maintaining low
costs. The A64 RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption.
The TMS470R1A64 device contains the following:
· ARM7TDMI 16/32-Bit RISC CPU
· TMS470R1x system module (SYS) with 470+ enhancements
· 64K-byte Flash
· 4K-byte SRAM
· Zero-pin phase-locked loop (ZPLL) clock module
· Analog watchdog (AWD) timer
· Real-time interrupt ( RTI) module
· Two serial peripheral interface (SPI) modules
· Two serial communication interface (SCI) modules
· Standard CAN controller (SCC)
· Class II serial interface (C2SIa)
· 10-bit multi-buffered analog-to-digital converter (MibADC), 8-input channels
· High-end timer (HET) controlling 13 I/Os
· External Clock Prescale (ECP)
· Up to 39 I/O pins and 1 input-only pin
The functions performed by the 470+ system module (SYS) include:
· Address decoding
· Memory protection
· Memory and peripherals bus supervision
· Reset and abort exception management
· Prioritization for all internal interrupt sources
· Device clock control
· Parallel signature analysis (PSA)
This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt
priority, and a device memory map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189).
The A64 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes.
The Flash memory on the A64 device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface.The Flash operates with a system clock frequency of up to 24 MHz. In pipeline mode, the Flash operates with a system clock frequency of up to 48 MHz. For more detailed nformation on the Flash, see the F05 Flash section of this data sheet and the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).
The A64 device has six communication interfaces: two SPIs, two SCIs, an SCC, and a C2SIa. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The SCC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy and harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed wiring. The C2SIa allows the A64 to transmit and receive messages on a class II network following an SAE J1850 (2) standard.
For more detailed functional information on the SPI, SCI, and SCC peripherals, see the specific TMS470R1x Peripheral Reference Guides (literature numbers SPNU195, SPNU196, and SPNU197, respectively). For more detailed functional information on the C2SIa peripheral, see the TMS470R1x Class II Serial Interface A (C2SIa)
Reference Guide (literature number SPNU218).
The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an
attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited
for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses.
For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199).
TMS470R1A64 Data Sheet
