TMS470PLF111

Supply voltage ranges: V_CC⁽²⁾ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V
Supply voltage ranges: V_CCIO, V_CCAD, V_CCP (flash pump)(2) . . . . . . . . . . . . . . . . . . . . . . . .  . −0.5 V to 6 V
Input voltage range: All input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  −0.5 V to 6 V
Input clamp current: ADIN[0:15] IIK (V_I < 0 or V_I > V_CCAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±10 mA
All other pins IIK (V_I < 0 or V_I > V_CCIOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .                             ±20 mA
Operating free-air temperature ranges, T_A: I version . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . −40 to 85
                                                               T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 to 105
                                                               Q version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 to 125
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 to 150
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. −65 to 150
1 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2 All voltage values are with respect to their associated grounds.

The TMS470PLF111(1) devices are members of the Texas Instruments TMS470 family of general-purpose16/32-bit reduced instruction set computer (RISC) microcontrollers. The TMS470PLF111 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The TMS470PLF111 utilizes the bigendian format where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte.

High-end embedded control applications demand more performance from their controllers while maintaining low costs. The TMS470PLF111 RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption.

The real-time interrupt (RTI) module on the TMS470PLF111 has the option to be driven by the oscillator clock. The digital watchdog (DWD) is a 25-bit resettable decrementing counter that provides a system reset when the watchdog counter expires.

The TMS470PLF111 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes.

The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface.The flash operates with a system clock frequency of up to 24 MHz. When in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz. For more detailed information on the flash, see the flash section of this data sheet. The flash on the TMS470PLF111 device can be protected by means of ECC. This feature utilizes a single error correction and double error detection circuit (SECDED circuit) to correct single bit errors and detect double bit errors for each 64-bits of data. This is achieved by maintaining an 8-bit ECC checksum/code for each 64-bit double-word of memory space in a separate ECC RAM memory space.

The TMS470PLF111 device has six communication interfaces: SPI, two LINs, CAN (SCC), C2SI, and I2C. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The LIN is the local interconnect network interface which also supports the SCI - a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The SCC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy and harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or multiplexed wiring. The C2SIb allows the PLF111 to transmit and receive messages on a class II network following an SAE Standard J1850 Class B Data Communication Network Interface standard. The I2C module is a multi-master communication module providing an interface between the PLF111 microcontroller and an I2C-compatible device via the I2C serial bus. The I²C supports both 100 Kbps and 400 Kbps speeds.

The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. TMS470PLF111 is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. The PLF111 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high- resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET.

The TMS470PLF111 device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be grouped by software for sequential conversion sequences. There are three separate groupings, all three of  which can be triggered by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode.

1 Throughout the remainder of this document, the TMS470PLF111 shall be referred to as either the full device name or PLF111. The frequency-modulated zero-pin phase-locked loop (FMZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 18). The function of the FMZPLL is to multiply the external frequency reference to a higher frequency for internal use. The FMZPLL provides the input to the global clock module (GCM). The GCM module subsequently provides system clock (HCLK), real-time interrupt clock (RTICLK), CPU clock (GCLK), HET clock (VCLK2) and peripheral interface clock (VCLK) to all other PLF111 device modules.

The TMS470PLF111 device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous external clock (ECLK). The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency.