TMS320VC5509A

Features:

High-Performance, Low-Power, Fixed-PointTMS320C55x Digital Signal Processor
− 9.26-, 6.95-, 5-ns Instruction Cycle Time
− 108-, 144-, 200-MHz Clock Rate
− One/Two Instruction(s) Executed per
Cycle
− Dual Multipliers [Up to 400 Million
Multiply-Accumulates per Second
(MMACS)]
− Two Arithmetic/Logic Units (ALUs)
− Three Internal Data/Operand Read Buses
and Two Internal Data/Operand Write Buses
 128K x 16-Bit On-Chip RAM, Composed of:
− 64K Bytes of Dual-Access RAM (DARAM)8 Blocks of 4K * 16-Bit
− 192K Bytes of Single-Access RAM
(SARAM) 24 Blocks of 4K * 16-Bit
 64K Bytes of One-Wait-State On-Chip ROM (32K * 16-Bit)
 8M * 16-Bit Maximum Addressable External
Memory Space (Synchronous DRAM)
 16-Bit External Parallel Bus Memory Supporting Either:
− External Memory Interface (EMIF) With
GPIO Capabilities and Glueless Interface to:
− Asynchronous Static RAM (SRAM)
− Asynchronous EPROM
− Synchronous DRAM (SDRAM)
− 16-Bit Parallel Enhanced Host-Port
Interface (EHPI) With GPIO Capabilities
 Programmable Low-Power Control of Six Device Functional Domains
 On-Chip Scan-Based Emulation Logic
 On-Chip Peripherals
− Two 20-Bit Timers
− Watchdog Timer
− Six-Channel Direct Memory Access (DMA) Controller
− Three Serial Ports Supporting a
Combination of:
− Up to 3 Multichannel Buffered Serial Ports (McBSPs)
− Up to 2 MultiMedia/Secure Digital Card
Interfaces
− Programmable Phase-Locked Loop Clock Generator
− Seven (LQFP) or Eight (BGA) General-
Purpose I/O (GPIO) Pins and a General-
Purpose Output Pin (XF)
− USB Full-Speed (12 Mbps) Slave Port
Supporting Bulk, Interrupt and
Isochronous Transfers − Inter-Integrated Circuit (I 2C) Multi-Master and Slave Interface
− Real-Time Clock (RTC) With Crystal
Input, Separate Clock Domain, Separate
Power Supply
− 4-Channel (BGA) or 2-Channel (LQFP)
10-Bit Successive Approximation A/D
 IEEE Std 1149.1† (JTAG) Boundary Scan
Logic
 Packages:
− 144-Terminal Low-Profile Quad Flatpack
(LQFP) (PGE Suffix)
− 179-Terminal MicroStar BGA™ (Ball Grid
Array) (GHH Suffix)
− 179-Terminal Lead-Free MicroStar BGA™
(Ball Grid Array) (ZHH Suffix)
 1.2-V Core (108 MHz), 2.7-V 3.6-V I/Os
 1.35-V Core (144 MHz), 2.7-V 3.6-V I/Os
 1.6-V Core (200 MHz), 2.7-V 3.6-V I/Os
 


Specifications

The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS. Figure 5−1 provides the test load circuit values for a 3.3-V I/O.
Supply voltage I/O range, DVDD   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . − 0.3 V to 4.0 V 
Supply voltage core range, CVDD . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .  − 0.3 V to 2.0 V
Input voltage range, VI   . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .  . . . . . .  − 0.3 V to 4.5 V
Output voltage range, VO  . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . .  . . . .   − 0.3 V to 4.5 V
Operating case temperature range, TC  . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . .− 40°C to 85°C
Storage temperature range Tstg − . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . ..  55°C to 150°C


Description

The TMS320VC5509A fixed-point digital signal processor (DSP) is based on the TMS320VC5509A DSP generation CPU processor core. The TMS320VC5509A DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The TMS320VC5509A CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.

The TMS320VC5509A CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.