TMS320VC5421

The TMS320VC5421 fixed-point digital signal processor (DSP) is a dual-core solution running at 200-MIPS performance. The TMS320VC5421 consists of two DSP subsystems capable of core-to-core communications and a 128K-word zero-wait-state on-chip program memory shared by the two DSP subsystems. Each subsystem consists of one '54x DSP core, 32K-word program/data DARAM, 32K-word data SARAM, 2K-word ROM, three multichannel serial interfaces, xDMA logic, one timer, one APLL, and other miscellaneous circuitry.

The TMS320VC5421 also contains a host-port interface (HPI) that allows the TMS320VC5421 to be viewed as a memory-mapped peripheral to a host processor. The TMS320VC5421 is pin-compatible with the TMS320VC5420.

Each subsystem has its separate program and data spaces, allowing simultaneous accesses to program instructions and data. Two read operations and one write operation can be performed in one cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. Furthermore, data can be transferred between program and data spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The '5421 includes the control mechanisms to manage interrupts, repeated operations, and function calls. In addition, the '5421 has 128K words of on-chip program memory that can be shared between the two subsystems.

The TMS320VC5421 is intended as a high-performance, low-cost, high-density DSP for remote data access or voice-over IP subsystems. TMS320VC5421 is designed to maintain the current modem architecture with minimal hardware and software impacts, thus maximizing reuse of existing modem technologies and development efforts.

NOTE: This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional
Overview (literature number SPRU307).