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TMS320VC5401

Features: Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators 17- * 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for No...

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SeekIC No. : 004525001 Detail

TMS320VC5401: Features: Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Indepen...

TMS320VC5401 Data Sheet

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Part Number:
TMS320VC5401
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

 Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
17- * 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
Data Bus With a Bus-Holder Feature
Extended Addressing Mode for 1M * 16-Bit Maximum Addressable External Program Space
4K x 16-Bit On-Chip ROM
8K x 16-Bit Dual-Access On-Chip RAM
Single-Instruction-Repeat and Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for Efficient Program and Data Management
  Instructions With a 32-Bit Long Word Operand
  Instructions With Two- or Three-Operand Reads
  Arithmetic Instructions With Parallel Store and Parallel Load
  Conditional Store Instructions
  Fast Return From Interrupt
  On-Chip Peripherals
−  Software-Programmable Wait-State Generator and Programmable Bank Switching
−  On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source
−  Two Multichannel Buffered Serial Ports (McBSPs)
−  Enhanced 8-Bit Parallel Host-Port Interface (HPI8)
−  Two 16-Bit Timers
−  Six-Channel Direct Memory Access (DMA) Controller
  Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
  CLKOUT Off Control to Disable CLKOUT
  On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1† (JTAG) Boundary Scan Logic
  20-ns Single-Cycle Fixed-Point Instruction Execution Time (50 MIPS) for 3.3-V Power Supply (1.8-V Core)
  144-Pin Plastic Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
  144-Ball MicroStar BGA (GGU Suffix)


Specifications

Supply voltage I/O range, DVDD  . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . −0.3 V to 4.0 V
Supply voltage core range, CVDD  . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . −0.3 V to 2.4 V
Input voltage range, VI  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.5 V
Output voltage range, VO  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.5 V
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . .  . . .  −40°C to 100°C
Storage temperature range, Tstg  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C


Description

The TMS320VC5401 fixed-point, digital signal processor (DSP) MS320VC5401 (hereafter referred to as the 5401 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor MS320VC5401 provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can be performed in a single machine cycle. In addition, the 5401 includes the control mechanisms to manage interrupts, repeated operations, and function calls.




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