TMS320UC5409

` Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
` 40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
` 17- * 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
` Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
` Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
` Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
`  Data Bus With a Bus-Holder Feature
`  Extended Addressing Mode for 8M * 16-Bit Maximum Addressable External Program Space
`  16K x 16-Bit On-Chip ROM
`  32K x 16-Bit Dual-Access On-Chip RAM
`  Single-Instruction-Repeat and Block-Repeat Operations for Program Code
`  Block-Memory-Move Instructions for Better Program and Data Management
`  Instructions With a 32-Bit Long Word Operand
`  Instructions With Two- or Three-Operand Reads
`  Arithmetic Instructions With Parallel Store and Parallel Load
`  Conditional Store Instructions
`  Fast Return From Interrupt
`  On-Chip Peripherals
   Software-Programmable Wait-State Generator and Programmable Bank Switching
   On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source
  Three Multichannel Buffered Serial Ports (McBSPs)
  Enhanced 8-Bit Parallel Host-Port Interface With 16-Bit Data/Addressing
  One 16-Bit Timer
  Six-Channel Direct Memory Access (DMA) Controller
`  Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
`  CLKOUT Off Control to Disable CLKOUT
`  On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1† (JTAG) Boundary Scan Logic
`  12.5-ns Single-Cycle Fixed-Point Instruction Execution Time (80 MIPS)
`  1.8-V Core Power Supply
`  1.8-V to 3.6-V I/O Power Supply Enables Operation With a SIngle 1.8-V Supply or With Dual Power Supplies
`  Available in a 144-Pin Plastic Thin Quad Flatpack (TQFP) (PGE Suffix) and a 144-Pin Ball Grid Array (BGA) (GGU Suffix)

absolute maximum ratings over specified temperature range (unless otherwise noted)†
Supply voltage I/O range, DV_DD‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0.3 V to 4.0 V
Supply voltage core range, CV_DD‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 2.0 V
Input voltage range, V_I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0.3 V to 4.5 V
Output voltage range, V_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4.5 V
Operating case temperature range, T_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 to 100
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 to 150

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

‡ All voltage values are with respect to V_SS.

The TMS320UC5409 fixed-point, digital signal processor (DSP) (hereafter referred to as the 'UC5409 unless otherwise specified) is ideal for low-power, high-performance applications. This processor offers very low power consumption and the flexibility to support various system voltage configurations. The wide range of I/O voltage enables it to operate with a single 1.8-V power supply or with dual power supplies for mixed voltage systems.

This feature eliminates the need for external level-shifting and reduces power consumption in emerging sub-3V systems.