TMS320LF2407

Features:

TMS320LF2407, TMS320LF2406, and TMS320LF2402 are Being Replaced by TMS320LF2407A, TMS320LF2406A, and TMS320LF2402A, Respectively. Hence, TMS320LF2407, TMS320LF2406, and TMS320LF2402 are NOT RECOMMENDED FOR NEW DESIGNS (NRND).
High-Performance Static CMOS Technology
  − 33-ns Instruction Cycle Time (30 MHz)
  − 30-MIPS Performance
  − Low-Power 3.3-V Design
Based on TMS320C2xx DSP CPU Core
  − Code-Compatible With F243/F241/C242
  − Instruction Set and Module Compatible With F240/C240
On-Chip Memory
  − Up to 32K Words x 16 Bits of Flash EEPROM (4 Sectors)
  − Up to 2.5K Words x 16 Bits of Data/Program RAM
    − 544 Words of Dual-Access RAM
    − Up to 2K Words of Single-Access RAM
Boot ROM
  − SCI/SPI Bootloader
Two Event-Manager (EV) Modules (EVA and EVB), Each Include:
  − Two 16-Bit General-Purpose Timers
  − Eight 16-Bit Pulse-Width Modulation (PWM) Channels Which Enable:
    − Three-Phase Inverter Control
    − Center- or Edge-Alignment of PWM Channels
    − Emergency PWM Channel Shutdown With External PDPINTx Pin
  − Programmable Deadband (Deadtime) Prevents Shoot-Through Faults
  − Three Capture Units For Time-Stamping of External Events
  − On-Chip Position Encoder Interface Circuitry
  − Synchronized Analog-to-Digital Conversion
  − Designed for AC Induction, BLDC, Switched Reluctance, and Stepper Motor Control
  − Applicable for Multiple Motor and/or Converter Control
External Memory Interface (LF2407)
  − 192K Words x 16 Bits of Total Memory: 64K Program, 64K Data, 64K I/O
Watchdog (WD) Timer Module
10-Bit Analog-to-Digital Converter (ADC)
  − 8 or 16 Multiplexed Input Channels
  − 500 ns Minimum Conversion Time
  − Selectable Twin 8-Input Sequencers Triggered by Two Event Managers
Controller Area Network (CAN) 2.0B Module
Serial Communications Interface (SCI)
16-Bit Serial Peripheral Interface (SPI) Module
Phase-Locked-Loop (PLL)-Based Clock Generation
Up to 40 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins
Up to Five External Interrupts (Power Drive Protection, Reset, and Two Maskable Interrupts)
Power Management:
  − Three Power-Down Modes
  − Ability to Power Down Each Peripheral Independently
Real-Time JTAG-Compliant Scan-Based Emulation, IEEE Standard 1149.1† (JTAG)
Development Tools Include:
  − Texas Instruments (TI) ANSI C Compiler, Assembler/Linker, and Code Composer Studio Debugger
  − Evaluation Modules
  − Scan-Based Self-Emulation (XDS510)
  − Broad Third-Party Digital Motor Control Support
Package Options
  − 144-Pin Low-Profile Quad Flatpack (LQFP) PGE (LF2407)
  − 100-Pin LQFP PZ (LF2406)
  − 64-Pin Quad Flatpack (QFP) PG (LF2402)
Extended Temperature Options (A and S)
  − A: − 40°C to 85°C
  − S: − 40°C to 125°C


Pinout




Specifications

Supply voltage range, V_DD, PLLV_CCA, V_DDO, and V_CCA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
V_CCP range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 5.5 V
Input voltage range, V_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
Output voltage range, V_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
Input clamp current, I_IK (V_IN < 0 or V_IN > V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Operating free-air temperature range, TA: A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 85°C
S version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 125°C
Junction temperature range, T_J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 150°C
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C

† Clamp current stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V_SS.


Description

The TMS320LF2407 devices, new members of the TMS320C24x generation of digital signal processor (DSP) controllers, are part of the TMS320LF2407 platform of fixed-point DSPs. The 240x† devices offer the enhanced TMS320LF2407 DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance processing capabilities. Several advanced peripherals, optimized for digital motor and motion control applications, have been integrated to provide a true single-chip DSP controller. While code-compatible with the existing C24x DSP controller devices, the TMS320LF2407 offers increased processing performance (30 MIPS) and a higher level of peripheral integration. See the TMS320x240x Device Summary section for device-specific features.

The TMS320LF2407 generation offers an array of memory sizes and different peripherals tailored to meet the specific price/performance points required by various applications. Flash devices of up to 32K words offer a cost-effective reprogrammable solution for volume production. Note that Flash-based devices contain a 256-word boot ROM to facilitate in-circuit programming. The 240x family also includes ROM devices that are fully pin-to-pin compatible with their Flash counterparts. (The ROM devices are described in the SPRS145 data sheet.)

All TMS320LF2407 devices offer at least one event manager module which has been optimized for digital motor control and power conversion applications. Capabilities of this module include center- and/or edge-aligned PWM generation, programmable deadband to prevent shoot-through faults, and synchronized analog-to-digital conversion. Devices with dual event managers enable multiple motor and/or converter control with a single 240x DSP controller.

The high-performance, 10-bit analog-to-digital converter (ADC) has a minimum conversion time of 500 ns and offers up to 16 channels of analog input. The autosequencing capability of the ADC allows a maximum of 16 conversions to take place in a single conversion session without any CPU overhead.

A serial communications interface (SCI) is integrated on all devices to provide asynchronous communication to other devices in the system. For systems requiring additional communication interfaces, the 2407 and 2406 offer a 16-bit synchronous serial peripheral interface (SPI). The 2407 and 2406 also offer a controller area network (CAN) communications module that meets 2.0B specifications. To maximize device flexibility, functional pins are also configurable as general-purpose inputs/outputs (GPIOs).

To streamline development time, JTAG-compliant scan-based emulation has been integrated into all devices. This provides non-intrusive real-time capabilities required to debug digital control systems. A complete suite of code-generation tools from C compilers to the industry-standard Code Composer Studio™ debugger supports this family. Numerous third-party developers not only offer device-level development tools, but also system-level design and development support.