TMS320DM647

` High-Performance Digital Media Processor
` C64x+ L1/L2 Memory Architecture  (DM647/DM648) 256K-bit (32K-byte) L1P Program Cache 720, 900-MHz C64x+™ Clock Rate [Direct Mapped] 1.39, 1.11-ns Instruction Cycle Time  256K-bit (32K-byte) L1D Data Cache 5760, 7200 MIPS [2-Way Set-Associative] Eight 32-Bit C64x+ Instructions/Cycle  2M-bit/256K-byte (DM647) or Fully Software-Compatible  With 4M-Bit/512K-byte) (DM648) L2 Unified C64x/Debug Mapped RAM/Cache [Flexible Allocation] Commercial Temperature Ranges
` Supports Little Endian Mode Only
` VelociTI.2™ Extensions to VelociTI™ ` Five Configurable Video Ports Advanced Very-Long-Instruction-Word (VLIW)  Providing a Glueless I/F to Common Video TMS320C64x+™ DSP Core Decoder and Encoder Devices Eight Highly Independent Functional Units  Supports Multiple Resolutions/Video Stds With VelociTI.2 Extensions:
` VCXO Interpolated Control Port (VIC)
` Six ALUs (32-/40-Bit), Each Supports  Supports Audio/Video Synchronization Single 32-bit, Dual 16-bit, or Quad 8-bit  
` External Memory Interfaces (EMIFs) Arithmetic per Clock Cycle 32-Bit DDR2 SDRAM Memory Controller
` Two Multipliers Support Four 16 x 16-bit With 256M-Byte Address Space (1.8-V I/O) Multiplies (32-bit Results) per Clock Cycle or Eight 8 x 8-bit Multiplies (16-Bit  Asynchronous 16-Bit Wide EMIF (EMIFA) Results) per Clock Cycle With up to 64M-Byte Address Reach Load-Store Architecture With Non-Aligned  Glueless Interface to Asynchronous Support Memories (SRAM, Flash, and EEPROM) 64 32-bit General-Purpose Registers  Synchronous Memories (SBSRAM and ZBT SRAM) Instruction Packing Reduces Code Size Supports Interface to Standard Sync All Instructions Conditional Devices and Custom Logic (FPGA, CPLD, Additional C64x+™ Enhancements ASICs, etc)
` Protected Mode Operation
` Enhanced Direct-Memory-Access (EDMA)
` Exceptions Support for Error Detection Controller (64 Independent Channels) and Program Redirection
` Hardware Support for Modulo Loop
` 3-Port Gigabit Ethernet Switch Subsystem Auto-Focus Module Operation
` Four 64-Bit General-Purpose Timers (Each
` C64x+ Instruction Set Features Configurable as Two 32-Bit Timers) Byte-Addressable (8-/16-/32-/64-bit Data)
` One UART (With RTS and CTS Flow Control) 8-bit Overflow Protection
` One 4-wire Serial Port Interface (SPI) With Two Bit-Field Extract, Set, Clear Chip-Selects Normalization, Saturation, Bit-Counting
` Master/Slave Inter-Integrated Circuit (I2C VelociTI.2 Increased Orthogonality Bus™) C64x+ Extensions
` Multichannel Audio Serial Port (McASP)
` Compact 16-bit Instructions  Ten Serializers and SPDIF (DIT) Mode
` Additional Instructions to Support 
` 16/32-Bit Host-Port Interface (HPI) Complex Multiplies
` 32-Bit 33-/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.3
` VLYNQ™ Interface (FPGA Interface)
` On-Chip ROM Bootloader

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.  hese are stress ratings only, and functional operation of the device at these or any other conditions beyond those  indicated under  ecommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device  eliability.
(2) All voltage values are with respect to VSS.

The TMS320C64x+™ DSPs (including the TMS320DM647/TMS320DM648 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320DM647 DM647/DM648 devices are based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The TMS320DM647 C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The TMS320DM647 C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 7200 million instructions per second (MIPS) at a clock rate of 900 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications.

The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The TMS320DM647 devices also have application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM647/DM648 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 256K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 4M-bit (DM648) or 2M-bit (DM647) memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: The DM647/DM648 TMS320DM647 device has five configurable 16-bit video port peripherals (VP0, VP1, VP2, VP3, and VP4). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The DM647/DM648 video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M), a VCXO interpolated control port (VIC); a 1000 Mbps Ethernet Switch Subsystem with a management data input/output (MDIO) module and two SGMII ports (DM648 only) or one SGMII port (only DM647); a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) bus interface; a multichannel audio serial port (McASP) with ten serializers; four 64-bit general-purpose timers each configurable as two independent 32-bit timers; a user-configurable 16-bit or 32-bit host-port interface (HPI); 32 pins for general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; one UART; and two glueless external memory interfaces: a synchronous and asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher DDR2 SDRAM interface.

The video port peripherals provide a glueless interface to common video decoder and encoder devices. The video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M).

The video port peripherals are configurable and can support either video capture and/or video display  modes. Each video port consists of two channels (A and B) with a 5120-byte capture/display buffer that is splittable between the two channels.

For more details on the video port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow the device to easily control peripheral modules and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM647/DM648 TMS320DM647 devices have a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.