TMS320C6727B

` C672x: 32-/64-Bit 350-MHz Floating-Point DSPs
` Upgrades to C67x+ CPU From C67x™ DSP Generation:
2X CPU Registers [64 General-Purpose]
New Audio-Specific Instructions
Compatible With the C67x CPU
` Enhanced Memory System
256K-Byte Unified Program/Data RAM
384K-Byte Unified Program/Data ROM
Single-Cycle Data Access From CPU
Large Program Cache (32K Byte) Supports RAM, ROM, and External Memory
` External Memory Interface (EMIF) Supports
133-MHz SDRAM (16- or 32-Bit)
Asynchronous NOR Flash, SRAM (8-,16-, or 32-Bit)
NAND Flash (8- or 16-Bit)
` Enhanced I/O System
High-Performance Crossbar Switch
Dedicated McASP DMA Bus
Deterministic I/O Performance
` dMAX (Dual Data Movement Accelerator) Supports:
16 Independent Channels
Concurrent Processing of Two Transfer Requests
1-, 2-, and 3-Dimensional Memory-to-Memory and Memory-to-Peripheral Data Transfers
Circular Addressing Where the Size of a Circular Buffer (FIFO) is not Limited to 2ⁿ
Table-Based Multi-Tap Delay Read and Write Transfers From/To a Circular Buffer
` Three Multichannel Audio Serial Ports
Transmit/Receive Clocks up to 50 MHz
Six Clock Zones and 16 Serial Data Pins
Supports TDM, I2S, and Similar Formats
DIT-Capable (McASP2)
` Universal Host-Port Interface (UHPI)
32-Bit-Wide Data Bus for High Bandwidth
Muxed and Non-Muxed Address and Data
` Two 10-MHz SPI Ports With 3-, 4-, and 5-Pin Options
` Two Inter-Integrated Circuit (I2C) Ports
` Real-Time Interrupt Counter/Watchdog
` Oscillator- and Software-Controlled PLL
` Applications:
Professional Audio
` Mixers
` Effects Boxes
` Audio Synthesis
` Instrument/Amp Modeling
` Audio Conferencing ` Audio Broadcast
` Audio Encoder
Emerging Audio Applications
Biometrics
Medical
Industrial
` Commercial or Extended Temperature
` 144-Pin, 0.5-mm, PowerPAD™ Thin Quad Flatpack (TQFP) [RFP Suffix]
` 256-Terminal, 1.0-mm, 16x16 Array Plastic Ball Grid Array (PBGA) [GDH and ZDH Suffixes]

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with referenced to V_SS unless otherwise specified.
(3) If OSCV_DD and OSCV_SS pins are used as filter pins for reduced oscillator jitter, they should not be connected to CV_DD and V_SS externally.

The TMS320C6727B  is the next generation of Texas Instruments' C67x generation of high-performance 32-/64-bit floating-point digital signal processors. The TMS320C6727B  includes the TMS320C6727B,TMS320C6726B, TMS320C6722B, and TMS320C6720 devices.(1) Enhanced C67x+ CPU. The C67x+ CPU is an enhanced version of the C67x CPU used on the C671x DSPs. TMS320C6727B  is compatible with the C67x CPU but offers significant improvements in speed, code density, and floating-point performance per clock cycle. At 350 MHz, the CPU is capable of a maximum performance of 2800 MIPS/2100 MFLOPS by executing up to eight instructions (six of which are floating-point instructions) in parallel each cycle. The CPU natively supports 32-bit fixed-point, 32-bit single-precision floating-point, and 64-bit double-precision floating-point arithmetic.

Efficient Memory System. The memory controller TMS320C6727B  maps the large on-chip 256K-byte RAM and 384K-byte ROM as unified program/data memory. Development is simplified since there is no fixed division between program and data memory size as on some other devices.

The memory controller TMS320C6727B  supports single-cycle data accesses from the C67x+ CPU to the RAM and ROM.Up to three parallel accesses to the internal RAM and ROM from three of the following four sources are supported:
· Two 64-bit data accesses from the C67x+ CPU
· One 256-bit program fetch from the core and program cache
· One 32-bit data access from the peripheral system (either dMAX or UHPI)