TMS320C6712

The TMS320C67xE DSPs (including the TMS320C6712 device) are the floating-point DSP family in the TMS320C6000E DSP platform. The TMS320C6712 (C6712) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 600 million floating-point operations per second (MFLOPS) at a clock rate of 100 MHz, the C6712 device is the lowest-cost DSP in the C6000E DSP platform. The C6712 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units.

The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The TMS320C6712 can produce two multiply-accumulates (MACs) per cycle for a total of 200 million MACs per second (MMACS).

The TMS320C6712 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, and a glueless 16-bit external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals.

The TMS320C6712 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a WindowsE debugger interface for visibility into source code execution.