Features: `Excellent Price/Performance Digital Signal Processors (DSPs): TMS320C67x
(TMS320C6711 and TMS320C6711B)
Eight 32-Bit Instructions/Cycle
C6211, C6211B, C6711, and C6711B are Pin-Compatible
100-, 150-MHz Clock Rates
10-, 6.7-ns Instruction Cycle Time
600, 900 MFLOPS
` VelociTI Advanced Very Long Instruction
Word (VLIW) C67x DSP Core (C6711/11B)
Eight Highly Independent Functional Units:
Four ALUs (Floating- and Fixed-Point)
Two ALUs (Fixed-Point)
Two Multipliers (Floating- and Fixed-Point)
Load-Store Architecture With 32 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
` Instruction Set Features
Hardware Support for IEEE Single-Precision and Double-Precision Instructions
Byte-Addressable (8-, 16-, 32-Bit Data)
8-Bit Overflow Protection
Saturation
Bit-Field Extract, Set, Clear
Bit-Counting
Normalization
` L1/L2 Memory Architecture
32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
` Device Configuration
Boot Mode: HPI, 8-, 16-, and 32-Bit ROM Boot
Endianness: Little Endian, Big Endian
` 32-Bit External Memory Interface (EMIF)
Glueless Interface to Asynchronous Memories: SRAM and EPROM
Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
512M-Byte Total Addressable External Memory Space
` Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
` 16-Bit Host-Port Interface (HPI)
Access to Entire Memory Map
` Two Multichannel Buffered Serial Ports (McBSPs)
Direct Interface to T1/E1, MVIP, SCSA Framers
ST-Bus-Switching Compatible
Up to 256 Channels Each
AC97-Compatible
Serial-Peripheral-Interface (SPI) Compatible (Motorola)
` Two 32-Bit General-Purpose Timers
` Flexible Phase-Locked-Loop (PLL) Clock Generator
` IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
` 256-Pin Ball Grid Array (BGA) Package (GFN Suffix)
` 0.18-m/5-Level Metal Process
CMOS Technology
` 3.3-V I/Os, 1.8-V InternalSpecificationsSupply voltage range, CVDD (see Note 1) ........................... 0.3 V to 2.3 V
Supply voltage range, DVDD (see Note 1) .............................0.3 V to 4 V
Input voltage range ........................................0.3 V to 4 V
Output voltage range .......................................0.3 V to 4 V
Operating case temperature ranges, TC:(default) .......................... 0 to 90
(A version) [C6711BGFNA only] ..................................40to105
Storage temperature range, Tstg .................................65 to 150
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
DescriptionThe TMS320C67x DSPs (including the TMS320C6711/C6711B devices) compose the floating-point DSP family in the TMS320C6000 DSP platform. The TMS320C6711 (C6711) and TMS320C6711B (C6711B) devices are based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.
With performance of up to 900 million floating-point operations per second (MFLOPS) at a clock rate of 150 MHz, the C6711/C6711B device also offers cost-effective solutions to high-performance DSP programming challenges. The C6711/C6711B DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The 6711/C6711B can produce two MACs per cycle for a total of 300 MMACS. The C6711/C6711B DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
The C6711/C6711B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.
The C6711/C6711B has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.
TMS320C671 Data Sheet
