TMS320C6455

` High-Performance Fixed-Point DSP (C6455)                                ` EDMA Controller (64 Independent Channels)
1.39-, 1.17-, 1-ns Instruction Cycle Time                                     ` Four 1x Serial RapidIO® Links (or One 4x),
720-, 850-MHz and 1-GHz Clock Rate v1.2 Compliant                  - 1.25-, 2.5-, 3.125-Gbps Link Rates
Eight 32-Bit Instructions/Cycle                                                      Message Passing, DirectIO Support, Error
5760, 6800, 8000 MIPS                                                                IEEE 1149.6 Compliant I/Os
5760, 6800, 8000 MMACS (16 Bits) Management Extensions, and Congestion
Commercial Temperature [0°C to 90°C] Control
` TMS320C64x+™ DSP Core                                  
Dedicated SPLOOP Instruction                                                      ` 32-/16-Bit Host-Port Interface (HPI)
Compact Instructions (32-/16-Bit)                                                 ` 32-Bit/66-MHz, 3.3-V Peripheral Component
Instruction Set Enhancements Interconnect (PCI) Master/Slave Interface
Exception Handling Conforms to PCI Specification 2.3
` TMS320C64x+ Megamodule                                                           ` One Inter-Integrated Circuit (I2C) Bus
` L1/L2 Memory Architecture:                                                            ` Two Multichannel Buffered Serial Ports
256K-Bit (32K-Byte) L1P Program Cache (McBSPs) [Direct  apped]                                                                                 ` 10/100/1000 Mb/s Ethernet MAC (EMAC)
256K-Bit (32K-Byte) L1D Data Cache                                              IEEE 802.3 Compliant
[2-Way Set-Associative]                                                                      Supports Multiple Media Independent
16M-Bit (2048K-Byte) L2 Unified Mapped Interfaces
RAM/Cache [Flexible Allocation] (MII, GMII, RMII, and RGMII)
` Enhanced Viterbi Decoder Coprocessor (VCP2)                               8 Independent Transmit (TX) and
Supports Over 694 7.95-Kbps AMR 8 Independent Received (RX) Channels
Programmable Code Parameters                                                     ` Two 64-Bit General-Purpose Timers,
` Enhanced Turbo Decoder Coprocessor (TCP2) Configurable as Four 32-Bit Timers
Supports up to Eight 2-Mbps 3GPP                                                   ` Universal Test and Operations PHY Interface
(6 Iterations) for ATM (UTOPIA)
Programmable Turbo Code and Decoding                                             UTOPIA Level 2 Slave ATM Controller
Parameters 8-Bit Transmit and Receive Operations up
` Endianess: Little Endian, Big Endian to 50 MHz per Direction
User-Defined Cell Format up to 64 Bytes                                                ` 64-Bit/133-MHz EMIFA
Glueless Interface to Asynchronous                                                        ` 16 General-Purpose I/O (GPIO) Pins
Memories (SRAM, Flash, and EPROM)                                                           ` PLL1 and PLL1 Controller
Glueless Interface to Synchronous                                                          ` PLL2 Dedicated for DDR2 EMIF and EMAC
Memories (SBSRAM and ZBT SRAM)                                                              ` IEEE-1149.1 (JTAG)
Supports Interface to Standard Sync Boundary-Scan-Compatible
Devices                                                                                                        ` 697-Pin Ball Grid Array (BGA) Package
Sync or Async Interface to Custom Logic (ZTZ Suffix), 0.8-mm Ball Pitch (FPGA, CPLD, ASICs, etc.)
32M-Byte Total Addressable External                                                      ` 0.09-m/7-Level Cu Metal Process (CMOS)
Memory Space (8MB per CE space)                                                              ` 3.3-, 1.8-, 1.5-, 1.2-V I/Os, 1.2-V Internal
` 32-Bit DDR2 EMIF (DDR2-500 SDRAM)

The TMS320C64x+™ DSPs (including the TMS320C6455 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6455 TMS320C6455 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs TMS320C6455 an excellent choice for applications including video and telecom infrastructures, imaging/medical, and wireless infrastructure (WI). The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

Based on 90-nm process technology and with performance of up to 8000 million instructions per second (MIPS) [or 8000 16-bit MMACs per cycle] at a clock rate of 1 GHz, the C6455 device offers cost-effective solutions to high-performance DSP programming challenges. The C6455 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors.

The C64x+ TMS320C6455 DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply throughout versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+ core. At a 1-GHz clock rate, this means 8000 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock cycle.