TMS320C6418GTS600

Program Memory Size :
Data RAM Size :
Number of Timers :
Maximum Operating Temperature : + 90 C
Mounting Style : SMD/SMT
Data Bus Width : 32 bit
Number of Programmable I/Os : 16
Core : TMS320
Operating Supply Voltage : 1.4 V
Maximum Clock Frequency : 600 MHz
Device Million Instructions per Second : 4800 MIPs
Package / Case : FCBGA-288


Features:

 High-Performance Fixed-Point DigitalSignal Processor (TMS320C6418)
−  Commercial Temperature Device
−  1.67-ns Instruction Cycle Time
−  600-MHz Clock Rate
−  4800 MIPS
−  Extended Temperature Device
−  2-ns Instruction Cycle Time
−  500-MHz Clock Rate
−  4000 MIPS
−  Eight 32-Bit Instructions/Cycle
−  Fully Software-Compatible With C64x™
  VelociTI.2™ Extensions to VelociTI™Advanced Very-Long-Instruction-Word
  (VLIW) TMS320C64x™ DSP Core
−  Eight Highly Independent Functional
   Units With VelociTI.2™ Extensions:
−  Six ALUs (32-/40-Bit), Each Supports
    Single 32-Bit, Dual 16-Bit, or Quad
    8-Bit Arithmetic per Clock Cycle
−  Two Multipliers Support Four 16 x 16-Bit Multiplies
 (32-Bit Results) per Clock Cycle orEight 8 x 8-Bit Multiplies
 (16-Bit Results) per Clock Cycle
−  Load-Store Architecture WithNon-Aligned Support
−  64 32-Bit General-Purpose Registers
−  Instruction Packing Reduces Code Size
−  All Instructions Conditional
  Instruction Set Features
−  Byte-Addressable (8-/16-/32-/64-Bit Data)
−  8-Bit Overflow Protection
−  Bit-Field Extract, Set, Clear
−  Normalization, Saturation, Bit-Counting
−  VelociTI.2™ Increased Orthogonality
  VelociTI.2™ Extensions to VelociTI™Advanced
     Very-Long-Instruction-Word(VLIW) TMS320C64x™ DSP Core
  Viterbi Decoder Coprocessor (VCP)
−  Supports Over 500 7.95-Kbps AMR VoiceChannels
−  Programmable Code Parameters
  L1/L2 Memory Architecture
−  128K-Bit (16K-Byte) L1P Program Cache(Direct Mapped)
−  128K-Bit (16K-Byte) L1D Data Cache(2-Way Set-Associative)
−  4M-Bit (512K-Byte) L2 Unified MappedRAM/Cache(Flexible RAM/Cache Allocation)
  Endianess: Little Endian, Big Endian
  32-Bit External Memory Interface (EMIF)
− Glueless Interface to AsynchronousMemories (SRAM and EPROM) and
   Synchronous Memories (SDRAM,
   SBSRAM, ZBT SRAM, and FIFO)
−  1024M-Byte Total Addressable ExternalMemory Space
  Enhanced Direct-Memory-Access (EDMA)Controller (64 Independent Channels)
  Host-Port Interface (HPI) [32-/16-Bit]
  Two Multichannel Audio Serial Ports (McASPs) - with Six Serial Data Pins each
  Two Inter-Integrated Circuit (I2C) Buses
−  Additional GPIO Capability
  Two Multichannel Buffered Serial Ports
  Three 32-Bit General-Purpose Timers
  Sixteen General-Purpose I/O (GPIO) Pins
  Flexible PLL Clock Generator
  On-Chip Fundamental Oscillator
  IEEE-1149.1 (JTAG†)Boundary-Scan-Compatible
  288-Pin Ball Grid Array (BGA) Package(GTS and ZTS Suffixes), 1.0-mm Ball Pitch
  0.13-µm/6-Level Cu Metal Process (CMOS)
  3.3-V I/Os, 1.4-V Internal (-600)
  3.3-V I/Os, 1.2-V Internal (A-500)


Specifications

Supply voltage ranges: CV_DD (see Note 1).................................... − 0.3 V to 1.8 V
                                     DV_DD (see Note 1)..........................................−0.3 V to 4 V
Input voltage range: V_I...................................................................... −0.3 V to 4 V
Output voltage range: V_O............................................. .................... −0.3 V to 4 V
Operating case temperature range, T_C: (default) [GTS and ZTS] .....−40to 105
(A version) [GTSA and ZTSA] .............................................................−40 to105
Storage temperature range, Tstg................................................ ....−65 to 150
Package Temperature Cycling: Temperature Range..........................−40 to125
Number of Cycles (GTS and ZTS)..................................................................... 1000
Number of Cycles (ZTS and ZTSA) .....................................................................500


Description

The TMS320C64x™ DSPs (including the TMS320C6418 device) TMS320C6418GTS600  are the highest-performance fixed-pointDSP generation in the TMS320C6000™ DSP platform. The TMS320C6418 (C6418) device is based on thesecond-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture(VelociTI.2™) developed by Texas Instruments (TI). The high-performance, lower-cost C6418 TMS320C6418GTS600  DSP enablescustomers to reduce system costs for telecom, software radio, Digital Terrestrial Television Broadcasting(DTTB), and digital Broadcast Satellite/Communication Satellite (BS/CS) applications. The C64x™ TMS320C6418GTS600  is acode-compatible member of the C6000™ DSP platform.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C6418device offers cost-effective solutions to high-performance DSP programming challenges. The C6418 DSPpossesses the operational flexibility of high-speed controllers and the numerical capability of arrayprocessors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length andeighthighly independent functional units-two multipliers for a 32-bit result and six arithmetic logicunits (ALUs)-with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional unitsinclude new instructionsto accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™architecture. The C6418 TMS320C6418GTS600  can produce four 16-bit multiply-accumulates (MACs) percycle for a total of2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of4800 MMACS. The C6418DSP TMS320C6418GTS600  also has application-specific hardware logic, on-chip memory, and additional onchip peripherals similarto the other C6000™ DSP platform devices.

The C6418 TMS320C6418GTS600  device has a high-performance embedded coprocessor [Viterbi Decoder Coprocessor (VCP)] thatsignificantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4can decode over 500 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supportsonstraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials,while generatinghard decisions or soft decisions. Communications between the VCP and the CPU are carried out through theEDMA controller.

he C6418 TMS320C6418GTS600  uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. TheLevel 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128Kbit2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 4-Mbit memory space thatisshared between program and data space. L2 memory can be configured as mapped memory, cache (up to256Kbytes), or combinations of the two. The peripheral set includes: two multichannel buffered audioserialports (McASPs); two inter-integrated circuit bus modules (I2Cs) ; two multichannel bufferedserial ports(McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bithost-port interface(HPI16/HPI32); a 16-pin general-purpose input/output port (GP0) with programmableinterrupt/eventgeneration modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacingto synchronous and asynchronous memories and peripherals.

Each McASP port supports one transmit and one receive clock zone, with six serial data pins which canbeindividually allocated to any of the two zones. The serial port supports time-division multiplexingoneach pinfrom 2 to 32 time slots. The C6418  TMS320C6418GTS600  has sufficient bandwidth to support all six serialdata pins transmitting a192-kHz stereo signal. Serial data in each zone may be transmitted andreceived on multiple serial data pinssimultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuitfor each high-frequency master clock which verifies that the masterclock is within a programmed frequencyrange.McASP also provides extensive error-checking and recoveryfeatures, such as the bad clock detection circuitfor each high-frequency master clock which verifies that the master clock is within a programmed frequencyrange.The C6418 has a complete set of development tools which includes: a new C compiler, an assembly optimizerto simplify programming and scheduling, and a Windows™ debuggerinterface for visibility into source codeexecution.

Parameters:

Technical/Catalog Information	TMS320C6418GTS600
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Package / Case	288-FCBGA
Packaging	Tray
Type	Fixed Point
Non-Volatile Memory	External
On-Chip RAM	544kB
Interface	Host Interface, I²C, McASP, McBSP
Voltage - I/O	3.30V
Voltage - Core	1.40V
Clock Rate	600MHz
Operating Temperature	0°C ~ 90°C
Drawing Number	296; 4205308; GTS; 288
Lead Free Status	Contains Lead
RoHS Status	RoHS Non-Compliant
Other Names	TMS320C6418GTS600 TMS320C6418GTS600 296 17480 ND 29617480ND 296-17480