TMS320C6416

` Highest-Performance Fixed-Point Digital Signal Processor (DSP) TMS320C6416
  2.5-, 2-, 1.67-ns Instruction Cycle Time
  400-, 500-, 600-MHz Clock Rate
  Eight 32-Bit Instructions/Cycle
  Twenty-Eight Operations/Cycle
  3200, 4000, 4800 MIPS
  Fully Software-Compatible With C62x
  Pin-Compatible With C6414/15 Devices
` VelociTI.2^TM Extensions to VelociTI Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x^TM DSP Core
  Eight Highly Independent Functional Units With VelociTI.2^TM Extensions:
  Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
  Non-Aligned Load-Store Architecture
  64 32-Bit General-Purpose Registers
  Instruction Packing Reduces Code Size
  All Instructions Conditional
` Instruction Set Features
  Byte-Addressable (8-/16-/32-/64-Bit Data)
  8-Bit Overflow Protection
  Bit-Field Extract, Set, Clear
  Normalization, Saturation, Bit-Counting
  VelociTI.2<sup>TM</sup> Increased Orthogonality
` Viterbi Decoder Coprocessor (VCP)
   Supports Over 500 7.95-Kbps AMR
  Programmable Code Parameters
` Turbo Decoder Coprocessor (TCP)
  Supports up to Six 2-Mbps 3GPP (6 Iterations)
  Programmable Turbo Code and Decoding Parameters
` L1/L2 Memory Architecture
  128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
  128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
  8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation)
` Two External Memory Interfaces (EMIFs)
  One 64-Bit (EMIFA), One 16-Bit (EMIFB)
   Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
  1280M-Byte Total Addressable External Memory Space
` Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
` Host-Port Interface (HPI)
  User-Configurable Bus-Width (32-/16-Bit)
` 32-Bit/33-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2
  Three PCI Bus Address Registers: Prefetchable Memory Non-Prefetchable Memory I/O
  Four-Wire Serial EEPROM Interface
  PCI Interrupt Request Under DSP Program Control
  DSP Interrupt Via PCI I/O Cycle
` Three Multichannel Buffered Serial Ports (McBSPs)
  Direct Interface to T1/E1, MVIP, SCSA Framers
  Up to 256 Channels Each
  ST-Bus-Switching-, AC97-Compatible
  Serial Peripheral Interface (SPI) Compatible (Motorola)
` Universal Test and Operations PHY Interface for ATM (UTOPIA)
  UTOPIA Level 2 Slave ATM Controller
  8-Bit Transmit and Receive Operations  up to 50 MHz per Direction
  User-Defined Cell Format up to 64 Bytes
` Sixteen General-Purpose I/O (GPIO) Pins
` Flexible PLL Clock Generator
` IEEE-1149.1 (JTAG†)Boundary-Scan-Compatible
` 532-Pin Ball Grid Array (BGA) Package (GLZ Suffix), 0.8-mm Ball Pitch
` 0.12-m/6-Level Metal Process (CMOS)
` 3.3-V I/Os, 1.2-V Internal (-400, -500 Speeds)
` 3.3-V I/Os, 1.4-V Internal (-600 Speed)

The TMS320C64x^TM DSPs (including the TMS320C6416 device) are the highest-performance fixed-point DSP generation in the TMS320C6000^TM DSP platform. The TMS320C6416 (C6416) TMS320C6416 device is based on the second-eneration high-performance, advanced VelociTI^TM very-long-instruction-word (VLIW) architecture (VelocTI.2^TM) dev eloped by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64x^TM is a code-compatible member of the C6000^TM DSP platform.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C6416 device offers cost-effective solutions to high-performance DSP programming challenges. The C6416 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors.

The C64x^TM DSP TMS320C6416 core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)- with VelociTI.2 extensions. The VelociTI.2^TM extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI architecture. The C6416 can produce two 32-bit multiply-accumulates (MACs) per cycle for a total of 1200 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6416 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000^TM DSP platform devices.

The C6416 TMS320C6416 has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) and Turbo
Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 500 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to thirty-six 384-Kbps or six 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable.

Communications between the VCP/TCP and the CPU are carried out through the EDMA controller.

The C6416 TMS320C6416 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes three multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 32-bit peripheral component interconnect (PCI); a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB†), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals.

The C6416 TMS320C6416 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows^TM debugger interface for visibility into source code execution.