TMS320C6415

Supply voltage ranges: CV_DD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 2.3 V
                                      DV_DD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4 V
Input voltage ranges: (except PCI), V_I . . . . . . . . . . . . . . . . . . . ...... . . . . . . 0.3 V to 4 V
                                    (PCI), V_IP . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to DV_DD + 0.5 V
Output voltage ranges: (except PCI), V_O . . . . . . . . . . . . . . . . . . . . . .  . . . . 0.3 V to 4 V
                                      (PCI), V_OP . . . . . . . . . . . . . . . . . ..... . . . 0.5 V to DVDD + 0.5 V
Operating case temperature range, T_C . . . . . . . . . . . . . . . . . . . . . . . .  ..... . . 0 to 90
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ......65to 150

The TMS320C64x DSPs (including the TMS320C6415 device) are the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The TMS320C6415 (C6415) device is based on the second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture (VelocTI.2) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64x is a code-compatible member of the C6000 DSP platform. With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C6415 device offers cost-effective solutions to high-performance DSP programming challenges. The C6415 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)- with VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI architecture. The C6415 can produce two 32-bit multiply-accumulates (MACs) per cycle for a total of 1200 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6415 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices.

The C6415 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes three multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB†), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals.

The C6415 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.