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TMS320C6211B

Features: Excellent Price/Performance Digital Signal Processors (DSPs): TMS320C62x (TMS320C6211 and TMS320C6211B)− Eight 32-Bit Instructions/Cycle− C6211, C6211B, C6711, and C6711B arePin-Compatible− 150-, 167-MHz Clock Rates− 6.7-, 6-ns Instruction Cycle Time− 1200, ...

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SeekIC No. : 004524910 Detail

TMS320C6211B: Features: Excellent Price/Performance Digital Signal Processors (DSPs): TMS320C62x (TMS320C6211 and TMS320C6211B)− Eight 32-Bit Instructions/Cycle− C6211, C6211B, C6711, and C6711B arePi...

TMS320C6211B Data Sheet

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Part Number:
TMS320C6211B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

Excellent Price/Performance Digital Signal Processors (DSPs): TMS320C62x (TMS320C6211 and TMS320C6211B)
− Eight 32-Bit Instructions/Cycle
− C6211, C6211B, C6711, and C6711B are
Pin-Compatible
− 150-, 167-MHz Clock Rates
− 6.7-, 6-ns Instruction Cycle Time
− 1200, 1333 MIPS
− Extended Temperature Device (C6211B)
VelociTI Advanced Very Long Instruction Word (VLIW) C62x DSP Core (C6211/11B)
− Eight Highly Independent Functional
Units:
− Six ALUs (32-/40-Bit)
− Two 16-Bit Multipliers (32-Bit Results)
− Load-Store Architecture With 32 32-Bit General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
Instruction Set Features
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
− Normalization
L1/L2 Memory Architecture
− 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
− 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
− 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
Device Configuration
− Boot Mode: HPI, 8-, 16-, and 32-Bit ROM Boot
− Endianness: Little Endian, Big Endian
32-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous Memories: SRAM and EPROM
− Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
− 512M-Byte Total Addressable External Memory Space
Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
16-Bit Host-Port Interface (HPI)
− Access to Entire Memory Map
Two Multichannel Buffered Serial Ports (McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral-Interface (SPI) Compatible (Motorola)
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked-Loop (PLL) Clock Generator
IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
256-Pin Ball Grid Array (BGA) Package (GFN and ZFN Suffixes)
0.18-m/5-Level Metal Process − CMOS Technology
3.3-V I/Os, 1.8-V Internal


Specifications

Supply voltage range, CVDD (see Note 1) . . . . . . . . . . . . . . . . . − 0.3 V to 2.3 V
Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to 4 V
Operating case temperature ranges, TC:(default) . . . . . . . . . . . . . . . 0 to 90                           
                                (A version) [C6211BGFNA only] . . . . . . . . . . . −40 to105
Storage temperature range, Tstg . . . . . . . . . . . . . .  . .  . . . . . . . .  −65to 150


Description

The TMS320C62x DSPs (including the TMS320C6211/C6211B devices) compose one of the fixed-point DSP families in the TMS320C6000 DSP platform. The TMS320C6211 (C6211) and TMS320C6211B (C6211B) TMS320C6211B devices are based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 1333 million instructions per second (MIPS) at a clock rate of 167 MHz, the C6211/C6211B TMS320C6211Bdevice offers cost-effective solutions to high-performance DSP programming challenges. The C6211/C6211B DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6211/C6211B TMS320C6211B can produce two multiply-accumulates (MACs) per cycle for a total of 333 million MACs per second (MMACS). The C6211/C6211B DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.




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