TMS320C6205

` High-Performance Fixed-Point Digital Signal Processor (DSP) − TMS320C6205
  − 5-ns Instruction Cycle Time
  − 200-MHz Clock Rate
  − Eight 32-Bit Instructions/Cycle
  − 1600 MIPS
` VelociTI Advanced-Very-Long-Instruction- Word (VLIW) TMS320C62x DSP Core
  − Eight Highly Independent Functional Units:
  − Six ALUs (32-/40-Bit)
  − Two 16-Bit Multipliers (32-Bit Result)
  − Load-Store Architecture With 32 32-Bit General-Purpose Registers
  − Instruction Packing Reduces Code Size
  − All Instructions Conditional
` Instruction Set Features
  − Byte-Addressable (8-, 16-, 32-Bit Data)
  − 8-Bit Overflow Protection
  − Saturation
  − Bit-Field Extract, Set, Clear
  − Bit-Counting
  − Normalization
` 1M-Bit On-Chip SRAM
  − 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
  − 512K-Bit Dual-Access Internal Data (64K Bytes)
  − Organized as Two 32K-Byte Blocks for Improved Concurrency
` 32-Bit External Memory Interface (EMIF)
  − Glueless Interface to Synchronous Memories: SDRAM or SBSRAM
  − Glueless Interface to Asynchronous Memories: SRAM and EPROM
  − 52M-Byte Addressable External Memory Space
` Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel
` Flexible Phase-Locked-Loop (PLL) Clock Generator
` 32-Bit/33-MHz Peripheral Component Interconnect (PCI) Master/Slave Interface
Conforms to: PCI Specification 2.2 Power Management Interface 1.1 Meets Requirements of PC99
   − PCI Access to All On-Chip RAM, Peripherals, and External Memory (via EMIF)
   − Four 8-Deep x 32-Wide FIFOs for Efficient PCI Bus Data Transfer
   − 3.3/5-V PCI Operation
   − Three PCI Bus Address Registers: Prefetchable Memory Non-Prefetchable Memory I/O
   − Supports 4-Wire Serial EEPROM Interface
   − PCI Interrupt Request Under DSP Program Control
   − DSP Interrupt Via PCI I/O Cycle
`  Two Multichannel Buffered Serial Ports (McBSPs)
   − Direct Interface to T1/E1, MVIP, SCSA Framers
   − ST-Bus-Switching Compatible
   − Up to 256 Channels Each
   − AC97-Compatible
   − Serial-Peripheral-Interface (SPI) Compatible (Motorola)
`  Two 32-Bit General-Purpose Timers 
`  IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
`  288-Pin MicroStar BGA Package (GHK Suffix)
`  0.15-m/5-Level Metal Process
   − CMOS Technology
`  3.3-V I/Os, 1.5-V Internal, 5-V Voltage Tolerance for PCI I/O Pins

absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Supply voltage ranges: CV_DD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 2.3 V
DV_DD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
(PCI), V_IOP (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
(PCI), V_DDP (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  −0.3 V to 4 V
Input voltage ranges: (except PCI), V_I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
(PCI), V_IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  −0.5 V to V_IOP + 0.5 V
Output voltage ranges: (except PCI), V_O . . . . . . . . . . . . . . . . . . . . . . . . . . .  −0.3 V to 4 V
(PCI), V_OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V_IOP + 0.5 V
Operating case temperature range, T_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 90
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  −65 to 150

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to V_SS.

The TMS320C62x DSPs (including the TMS320C6205 device) compose the fixed-point DSP generation in the TMS320C6000 DSP platform. The TMS320C6205 (C6205) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making the C6205 an excellent choice for multichannel and multifunction applications.

With performance of up to 1600 million instructions per second (MIPS) at a clock rate of 200 MHz, the C6205 offers cost-effective solutions to high-performance DSP-programming challenges. The C6205 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units.

The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6205 can produce two multiply-accumulates (MACs) per cycle for a total of 400 million MACs per second (MMACS). The C6205 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6205 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space.

Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a peripheral component interconnect (PCI) module that supports 33-MHz master/slave interface and 4-wire serial EEPROM interface, and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The C6205 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.