TMS320C30

Features:

` High-Performance Floating-Point Digital Signal Processor (DSP)
TMS320C30-50 (5 V) 40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS
TMS320C30-40 (5 V) 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS
TMS320C30-33 (5 V) 60-ns Instruction Cycle Time 183.3 MOPS, 33.3 MFLOPS, 16.7 MIPS
TMS320C30-27 (5 V) 74-ns Instruction Cycle Time 148.5 MOPS, 27 MFLOPS, 13.5 MIPS
` 32-Bit High-Performance CPU
` 16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations
` 32-Bit Instruction Word, 24-Bit Addresses
` Two 1K * 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks
` One 4K * 32-Bit Single-Cycle Dual-Access On-Chip ROM Block
` On-Chip Memory-Mapped Peripherals:
Two Serial Ports
Two 32-Bit Timers
One-Channel Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation
` Two 32-Bit External Ports
` 24- and 13-Bit Addresses
` 0.7-mm Enhanced Performance Implanted CMOS (EPICE) Technology
` 208-Pin Plastic Quad Flat Package (PPM Suffix)
` 181-Pin Grid Array Ceramic Package (GEL Suffix)
` Eight Extended-Precision Registers
` Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
` Two- and Three-Operand Instructions
` Parallel Arithmetic and Logic Unit (ALU) and Multiplier Execution in a Single Cycle
` Block-Repeat Capability
` Zero-Overhead Loops With Single-Cycle Branches
` Conditional Calls and Returns
` Interlocked Instructions for Multiprocessing Support
` Two Sets of Memory Strobes (STRB and MSTRB) and One I/O Strobe (IOSTRB)
` Separate Bus-Control Registers for Each Strobe-Control Wait-State Generation


Specifications

Supply voltage range, V_CC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0.3 V to 7 V
Input voltage range, V_I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V
Output voltage range, V_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 0.3 V to 7 V
Continuous power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15 W
Operating case temperature range, T_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .    . 0to 85Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . .   55 to 150

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:
1. All voltage values are with respect to V_SS.
2. Actual operating power is less. This value is obtained under specially produced worst-case test conditions, which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to both primary and extension buses at the maximum rate possible. See normal (I_CC) current specification in the electrical characteristics table and also read Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRA020).


Description

The TMS320C30 is the newest member of the TMS320C3x generation of DSPs from Texas Instruments (TIE). The TMS320C30 is a 32-bit floating-point processor manufactured in 0.7-mm triple-level-metal CMOS technology.

The TMS320C30's internal busing and special DSP instruction set have the speed and flexibility to execute up
to 50 MFLOPS (million floating-point operations per second). The TMS320C30 optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.

The TMS320C30 can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are results of these features.

General-purpose applications are enhanced greatly by the large address space, multiprocessor interface, internally and externally generated wait states, two external interface ports, two timers, serial ports, and multiple interrupt structure. The TMS320C30 supports a wide variety of system applications from host processor to dedicated coprocessor.