TMS29LF008T

` Single Power Supply Supports 2.7-V and 3.6-V Read/Write Operation
` Organization . . . 1048576 By 8 Bits
` Array Blocking Architecture One 16K-Byte Boot Sector Two 8K-Byte Parameter Sectors One 32K-Byte Sector Fifteen 64K-Byte Sectors Any Combination of Sectors Can Be Erased. Supports Full-Chip Erase Any Combination of Sectors Can Be Marked as Read-Only
` Boot-Code Sector Architecture T = Top Sector B = Bottom Sector
` Sector Protection Hardware Protection Method That Disables Any Combination of Sectors From Write or Erase Operations Using Standard Programming Equipment
` Embedded Program/Erase Algorithms Automatically Pre-Programs and Erases Any Sector Automatically Programs and Verifies the Program Data at Specified Address
` JEDEC Standards Compatible With JEDEC Byte Pinouts Compatible With JEDEC EEPROM Command Set
` Fully Automated On-Chip Erase and Program Operations
` 100 000 Program/Erase Cycles
` Low Power Dissipation
` Low Current Consumption 20-mA Typical Active Read for Byte Mode 30-mA Typical Program/Erase Current Less Than 60-mA Standby Current 5 mA in Deep Power-Down Mode
` All Inputs/Outputs TTL-Compatible
`Erase Suspend/Resume Supports Reading Data From, or Programming Data to, a Sector Not Being Erased
` Hardware-Reset Pin Initializes the Internal-State Machine to the Read Operation - 40-Pin Thin Small-Outline Package (TSOP) (DCD Suffix)
` Detection Of Program/Erase Operation Data Polling and Toggle Bit Feature of Program/Erase Cycle Completion Hardware Method for Detection of Program/Erase Cycle Completion Through Ready/Busy (RY/BY) Output Pin
`High-Speed Data Access at 3.3-V VCC
10% at Three Temperature Ranges 90 ns Commercial . . . 0°C to 70°C 100 ns Extended . . . 40°C to 85°C 120 ns Automotive . . . 40°C to 125°C

Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 V to 7 V
Input voltage range: All inputs except A9, CE, OE (see Note 2) . . . . . . . . . . . . . . . . . . . . 0.6 V to VCC + 1 V
A9, CE, OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 V to 13.5 V
Output voltage range (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 V to VCC + 1 V
Ambient temperature range during read/erase/program, TA
(L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
(E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 85°C
(Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C


† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:
1. All voltage values are with respect to VSS.
2. The voltage on any input pin can undershoot to 2 V for periods less than 20 ns (see Figure 4).
3. The voltage on any input or output pin can overshoot to 7 V for periods less than 20 ns (see Figure 5).

The TMS29LF008T/B is an 1048576 by 8-bit (8388608-bit), 3-V single-supply, programmable read-only memory device that can be electrically erased and reprogrammed. This device is organized as 1024K by 8 bits, divided into 19 sectors:
One 16K-byte boot sector
Two 8K-byte sectors
One 32K-byte sector
Fifteen 64K-byte sectors
Any combination of sectors can be marked as read-only or erased. Full-chip erasure is also supported. Sector data protection is afforded by methods that can disable any combination of sectors from write or read operations using standard programming equipment. An on-chip state machine controls the program and erase operations by providing an on-board algorithm that automatically pre-programs and erases any sector before it automatically programs and verifies program data at any specified address. The command set is compatible with that of the Joint Electronic Device Engineering Council (JEDEC) standards and is compatible with the JEDEC 8M-bit electrically erasable, programmable read-only memory (EEPROM) command set. A suspend/resume feature allows access to unaltered memory blocks during a section-erase operation. All outputs of this device are TTL-compatible. Additionally, an erase/suspend/resume feature supports reading data from, or programming data to, a sector that is not being erased.