TMS29F002RT

` Single Power Supply Supports 5-V
10% Read/Write Operation
` Organization : . . . 262144 by 8 Bits
`Array-Blocking Architecture One 16K-Byte Boot Sector Two 8K-Byte Parameter Sectors One 32K-Byte Sector Three 64K-Byte Sectors Any Combination of Sectors Can Be Erased. Support Full-Chip Erase Any Combination of Sectors Can Be Marked as Read-Only
` Boot-Code Sector Architecture T = Top Sector B = Bottom Sector
` Sector Protection Hardware Protection Method That Disables Any Combination of Sectors From Write or Erase Operations Using Standard Programming Equipment
` Embedded Program/Erase Algorithms Automatically Pre-Programs and Erases Any Sector Automatically Programs and Verifies the Program Data at Specified Address
` JEDEC Standards Compatible With JEDEC Byte Pinouts Compatible With JEDEC EEPROM Command Set
` Fully Automated On-Chip Erase and Program Operations
` 100 000 Program/Erase Cycles
` Low Power Dissipation
` Low Current Consumption 25-mA Typical Active Read 30-mA Typical Program/Erase Current Less Than 100-mA Standby Current
` All Inputs/Outputs TTL-Compatible
` Erase Suspend/Resume Supports Reading Data From, or Programming Data to, a Sector Not Being Erased
` Hardware-Reset Pin Initializes the Internal-State Machine to the Read Operation
` 32-Pin Plastic Leaded Chip Carrier (PLCC) (FM Suffix)
` Detection Of Program/Erase Operation Data Polling and Toggle Bit Feature of Program/Erase Cycle Completion
` High-Speed Data Access at 5-V VCC
10% 90 ns Commercial . . . 0°C to 70°C 100 ns Extended . . . 40°C to 85°C

Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 V to 7 V
Input voltage range: All inputs except A9, CE, OE (see Note 2) . . . . . . . . . . . . . . . . . . . . 0.6 V to VCC + 1 V
A9, CE, OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 V to 13.5 V
Output voltage range (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 V to VCC + 1 V
Ambient temperature range during read/erase/program, TA
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 85°C
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C


† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:
1. All voltage values are with respect to VSS.
2. The voltage on any input pin can undershoot to 2 V for periods less than 20 ns (see Figure 10).
3. The voltage on any output pin can overshoot to VCC + 2 V for periods less than 20 ns (see Figure 11).

The TMS29F002RT/B is a 262144 by 8-bit (2097152-bit), 5-V single-supply, programmable read-only memory device that can be electrically erased and reprogrammed. This device is organized as 262144 by 8 bits, divided into seven sectors:
One 16K-byte boot sector
Two 8K-byte sectors
One 32K-byte sector
Three 64K-byte sectors
Any combination of sectors can be marked as read-only or erased. Full-chip erasure is also supported. Sector data protection is afforded by methods that can disable any combination of sectors from write or read operations using standard programming equipment. An on-chip state machine provides an on-board algorithm that automatically pre-programs and erases any sector before it automatically programs and verifies program data at any specified address. The command set is compatible with the JEDEC 2M-bit electrically erasable, rogrammable read-only memory (EEPROM) command set. A suspend/resume feature allows access to unaltered memory blocks during a section-erase operation. All outputs of this device are TTL-compatible. Additionally, an erase/suspend/resume feature supports reading data from, or programming data to, a sector that is not being erased.

Device operations are selected by writing JEDEC-standard commands into the command register using standard microprocessor write timings. The command register acts as an input to an internal-state machine which interprets the commands, controls the erase and programming operations, outputs the status of the device, outputs the data stored in the device, and outputs the device algorithm-selection code. On initial power up, the device defaults to the read mode. A hardware-reset pin initializes the internal-state machine to the read  eration.

The device has low power dissipation with a 25-mA typical active read for the byte mode, 30-mA typical rogram/erase current mode, and less than 100-
A standby current with a 15-
A deep-power-down mode. These devices are offered with 90-, 100-, and 120-ns access times. Table 1 and Table 2 show the sector-address ranges. The TMS29F002RT/B is offered in a 32-pin plastic leaded chip carrier (PLCC) (FM suffix).