Features: • TX49/H4 Processor Core TX49/H4 Processor Core is a 64-bit RISC CPU core Toshiba developed based on the architecture of MIPS for interactive consumer applications including Printer, Network and set-top terminals.• Internal bus width is 64-bit, External bus width is 64-bit or...
TMPR4956C: Features: • TX49/H4 Processor Core TX49/H4 Processor Core is a 64-bit RISC CPU core Toshiba developed based on the architecture of MIPS for interactive consumer applications including Printer,...
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Features: Maps signals in one of the following ways:- Maps up to 28 asynchronous DS1 signals to SO...
Parameter | Symbol | Ratings | Unit |
Supply Voltage (I/O) Supply Voltage (Core) Input Voltage (Note 2) Storage Temperature |
VCCIOMax VCCIntMax VIN TSTG |
−0.3 to 3.9 −0.3 to 2.0 −0.3 to VCCIO + 0.3 −40 to + 125 |
V V V °C |
Note1: The absolute maximum ratings are rated values that must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
Note 2: Even VCCIO + 0.3 shall not exceed the VCCIOMax rating.
TX4956 has two types of system interface. One is for R5000 type protocol , other is for R4300 type protocol, R5000 type protocol supports two bus widths, 32-bit bus width and 64-bit bus width. R4300 type protocol only supports 32-bit bus width, Operation with 32-bit bus width on either R5000 or R4300 type protocol is called "32-bit mode". Operation with 64-bit bus width on R5000 is called "64-bit mode". And especially we call operation of R5000 type protocol with 32-bit width "TX4955 mode" which means TX4955 compatible. Table 2.2.1 shows the relation between System Interface operation modes and pin settings .