TMPR4955A

• TX49/H2 Processor Core
TX49/H2 Processor Core is a 64-bit RISC CPU core Toshiba developed based on the architecture of MIPS for interactive consumer applications including Printer, Network and set-top terminals.
• IEEE754 compatible single and double precision FPU
The floating-point operations fully conform to the requirements of ANSI/IEEE Standard 754-1985, IEEE Standard for Binary Floating-Point Arithmetic.As 32 general purpose register (32 FGRs), each of which is 64 bits wide and 2 control of
FPU registers (2 FCRs), each of which is 32bit wide. All floating-point instructions, as defined in the MIPS ISA for the floating-point coprocessor, CP1, are processed by the other hardware unit that executes integer instruction.
• Internal bus width is 64-bit, External bus width is 32-bit
Core and Cache are connect with 64-bit Internal bus. External bus is SysAD-bus I/F. This interface is compatible with the TX4300, R4000, and R5000 system interfaces.
• Power management
Internal: 1.5 V I/O: 3.3 V The TX49/H2 Processor support Power management mode (Halt, Doze)
• Maximum operating frequency
The TX49/H2 Processor's maximum operating frequency is 200 MHz.The SysAD-bus I/F and TX49/H2 Processor's maximum operating frequency is set by External pin (DivMode (1:0)).
• Package
TX4955A: 160-pin QFP
• Part Number
TMPR4955AF-167
TMPR4955AF-200

Supply voltage (for I/O) VccIOMax ..............−0.5 ∼ 3.9 V
Supply voltage (for internal) VccIntMax ......−0.5 ∼ 3.0 V
Input voltage ^(*1) V_IN ...................−0.5 ∼ V_CCIO + 0.3 V
Storage Temperature T_STG .....................−65 ∼ + 150
Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when
designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
(*1) V_IN Min = −1.5 V for pulse width less than 10 ns.