TMPR4925

• TX49/H2 core with an integrated IEEE 754-compliant FPU for single- and double-precision operations
• 4-channel SDRAM Controller (32 bit/80 MHz) and support SyncFlash® memory
• 6-channel External Bus Controller (including 2-slot PCMCIA Interface)
• NAND Flash Controller
• 32-bit PCI Controller (33 MHz)
• 4-channel Direct Memory Access (DMA) Controller
• 2-channel Serial I/O Port
• Parallel I/O Port (up to 32-bit)
• SPI (Serial Peripheral Interface)
• CHI (high-speed serial Concentration Highway Interface)
• Interrupt Controller
• 3-channel Timer/Counter and 44-bit up-counter RTC
• AC-Link Controller
• PCMCIA Interface (2-slot)
• Supports selection between little endian and big endian modes
• Low power dissipation The TX4925 operates with the 1.5 V core and the 3.3 V I/O, while supporting a low-power (Halt) mode.
• CPU maximum operating frequency: 200 MHz
• IEEE1149.1 (JTAG) support: Debug Support Unit (Enhanced JTAG)
• 256-pin PBGA package

Supply voltage (for I/O) V_CCIOMax ................−0.3 ~ 3.9 V
Supply voltage (for internal) V_CCIntMax........ −0.3 ~ 3.0 V
Input voltage (*2) V_IN .....................−0.3 ~ V_CCIO + 0.3 V
Storage Temperature T_STG .........................−40 ~ +125
*1: If LSI is used above the maximum ratings, permanent destruction of LSI can result. In addition,it is desirable to use LSI for normal operation under the recommended condition. If these conditions are exceeded, reliability of LSI may be adversely affected.
*2: The maximum rated VCCIOMax voltage must not be exceeded even at VCCIO + 0.3 volts.