DescriptionThe TMPR3912XB-75 is a single-chip integrated digital ASSP for PDA(Personal Digital Assistants).The TMPR3912XB-75 consists of PDA system support logic, integrated with the TX39 processor Core designed by Toshiba.The TMPR3912XB-75 consists of PDA system support logic, integrated with the...
TMPR3912XB-75: DescriptionThe TMPR3912XB-75 is a single-chip integrated digital ASSP for PDA(Personal Digital Assistants).The TMPR3912XB-75 consists of PDA system support logic, integrated with the TX39 processor ...
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Features: Maps signals in one of the following ways:- Maps up to 28 asynchronous DS1 signals to SO...
The TMPR3912XB-75 is a single-chip integrated digital ASSP for PDA(Personal Digital Assistants).The TMPR3912XB-75 consists of PDA system support logic, integrated with the TX39 processor Core designed by Toshiba.The TMPR3912XB-75 consists of PDA system support logic, integrated with the TX39 processor core designed by Toshiba. For details of the system support logic and the TX39 processor core, refer to the user's manual and TX39 family user's manual, respectively.
The TMPR3912XB-75 has the following features including:(1)toshiba has added its own multiply-add and branch-likely instructions;(2)a single-cycle multiply/accumulate module to allow integrated DSP functions, such as a software modem for high-performance standard data and fax protocols;(3)instruction cache: 4K bytes; data cache:1K bytes;(4)on-chip translation lookaside buffer (TLB) with 32x64-bit wide entries, each of which maps 4KByte page Max 75MHz operation;(5)clock generator with built-in eightfold-frequency phase-locked loop (PLL);(6)four-stage write buffer;(7)a high performance and flexible bus interface unit;(8)multiple DMA channels;(9)memory controller for DRAM, HDRAM, SDRAM, SRAM, ROM, Flash Memory and PCMCIA;(10)power management unit.
The absolute maximum ratings of the TMPR3912XB-75 are:(1)input voltage:Vss-0.5 to Vdd+0.5 V;(2)storage temperature:-55 to 125;(3)maximum dissipation:1W;(4)supply voltage:Vss-0.5 to 4.5V.The TMPR3912XB-75 incorporates a 4K-byte instruction cache and a 1K-byte data cache. The instruction cache is direct-mapped with a block size of 16 bytes. The data cache uses two-way set-associative mapping with a block size of four bytes. The data cache has a lock function that locks data in one direction.The write-through method is used to write data back to memory.These pins are multi-function input/output ports. Each port can be independently programmed as an input or output port, or can be programmed for multi-function use to support test signals (for debugging purposes only). Each port can generate a separate positive and negative edge interrupt. Note that 30 other multi-function pins are available for usage as multi-function input/output ports.These pins are named after their respective standardlnormal function and are not listed here.