TMPR3912AU

The TMPR3912AU is a single-chip integrated digital ASSP for PDA(personal digital assistants). The TMPR3912AU consists of PDA system support logic, integrated with the TX39 processor Core designed by Toshiba.The TMPR3912AU consists of PDA system support logic, integrated with the TX39 Processor Core designed by Toshiba.For details of the system support logic and the TX39 processor Core, refer to the User's manual and TX39 family user's manual, respectively.

The TMPR3912AU has the following features including:(1)toshiba has added its own multiply-add and branch-likely instructions;(2)a single-cycle multiply/accumulate module to allow integrated DSP functions, such as a software modem for high-performance standard data and fax protocols;(3)instruction cache: 4K bytes; data cache:1K bytes;(4)on-chip translation lookaside buffer (TLB) with 32x64-bit wide entries, each of which maps 4KByte page Max 75MHz operation;(5)clock generator with built-in eightfold-frequency phase-locked loop (PLL);(6)four-stage write buffer;(7)a high performance and flexible bus interface unit;(8)multiple DMA channels;(9)memory controller for DRAM, HDRAM, SDRAM, SRAM, ROM, Flash Memory and PCMCIA;(10)power management unit.

The absolute maximum ratings of the TMPR3912AU are:(1)input voltage:Vss-0.5 to Vdd+0.5 V;(2)storage temperature:-55 to 125;(3)maximum dissipation:1W;(4)supply voltage:Vss-0.5 to 4.5V.The TMPR3912AU incorporates a 4K-byte instruction cache and a 1 K-byte data cache. The instruction cache is direct-mapped with a block size of 16 bytes. The data cache uses two-way set-associative mapping with a block size of four bytes. The data cache has a lock function that locks data in one direction. The write-through method is used to write data back to memory.This pin is the master clock source for the SIB logic. This pin is available for use in one of two modes. First, SIBMCLK can be configured as a high-rate output master clock source required by certain external codec devices. In this mode all SIB clocks are synchronously slaved to the main TMPR3912AU system clock CLK2X. Conversely, SIBMCLK can be configured as an input slave clock source.In this mode, all SIB clocks are derived from an external SIBMCLK oscillator source, which is asynchronous with respect to CLK2X. Also, for this mode,SIBMCLK can still be optionally used as a high-rate master clock source required by certain external codec devices.