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TMP92CM27

Features: 1) Double buffer (Transmit/Receive)2) Generate CRC7 and CRC16 of Transmit/Receive data3) Baud Rate : 10Mbps max4) MSB/LSB-first5) 8/16bit data length6) Clock Rising/Falling edge7) The interruption function of each 1 channel : INTHSC0/INTHSC1Read, Mask, Clear interrupt and Clear enable ca...

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SeekIC No. : 004524699 Detail

TMP92CM27: Features: 1) Double buffer (Transmit/Receive)2) Generate CRC7 and CRC16 of Transmit/Receive data3) Baud Rate : 10Mbps max4) MSB/LSB-first5) 8/16bit data length6) Clock Rising/Falling edge7) The inte...

TMP92CM27 Data Sheet

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Part Number:
TMP92CM27
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

1) Double buffer (Transmit/Receive)
2) Generate CRC7 and CRC16 of Transmit/Receive data
3) Baud Rate : 10Mbps max
4) MSB/LSB-first
5) 8/16bit data length
6) Clock Rising/Falling edge
7) The interruption function of each 1 channel : INTHSC0/INTHSC1
Read, Mask, Clear interrupt and Clear enable can control each 4 interrupts:
RFR0/1 (Receive buffer of HSC0RD/HSC1RD: Full),
RFW0/1 (Transmission buffer of HSC0TD/HSC1TD: Empty),
REND0/1 (Receive buffer of HSC0RS/HSC1RS: Full),
TEND0/1 (Transmission buffer of HSC0TS/HSC1TS: Empty).
RFR0/1, RFW0/1 can high-speed transaction by micro DMA.




Specifications

Symbol Contents Rating Unit
AVCC Power Supply Voltage -0.5 to 4.0 V
VIN Input Voltage -0.5 to VCC+0.5 V
IOL Output Current (1pin) 2 mA
IOH Output Current (1pin) -2 mA
IOL Output Current (total) 80 mA
IOH Output Current (total) -80 mA
PD Power Dissipation (Ta = 85) 600 mW
TSOLDER Soldering Temperature (10s) 260
TSTG Storage Temperature -65 to 150
TOPR Operation Temperature -40 to 85

Note: The maximum ratings are rated values that must not be exceeded during operation,even for an instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its performance may be degraded,causing it to catch fire or explode resulting in injury to the user. Thus, when designing products that include this device, ensure that no maximum rating value will ever be exceeded






Description

Access controller is enabled when SDACR1<SMAC> = 1. And then SDRAM control signals ( SDCS , SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM, SDCLK and SDCKE) are operating during the time CPU accesses CS3 area. 

In the access cycle, outputs row/column multiplex address through A0 to A15 pin.

And multiplex width is decided by setting SDACR2<SMUXW0:1>. The relation between multiplex width and row/column address is shown in Table.






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