TMP92CF26AXBG

Operating Supply Voltage :
Operating Temperature Range :
Data Bus Width : 32 bit
On-Chip ADC : Yes
Mounting Style : SMD/SMT
Maximum Clock Frequency : 80 MHz
Core : TLCS-900
Processor Series : TLCS-900
Data RAM Size : 144 KB
Package / Case : FBGA
Program Memory Size : 8 KB


Features:

The TMP92CF26A is a high-speed advanced 32-bit microcontroller developed for controlling equipment which processes mass data.
The TMP92CF26AXBG is housed in a 228-pin BGA package.
(1) CPU: 32-bit CPU (High-speed 900/H1 CPU)
• Compatible with TLCS-900/L1 instruction code
• 16 Mbytes of linear address space
• General-purpose register and register banks
• Micro DMA: 8channels (62.5 ns/4 bytes at fSYS = 80 MHz, best case)
(2) Minimum instruction execution time: 12.5 ns (at fSYS = 80 MHz)
(3) Internal RAM: 144 Kbytes (can be used for program, data and display memory) Internal ROM: 8 Kbytes (memory for Boot only) Possible downloading of user program through either USB, UART.

Specifications

Symbol	Contents	Rating	Unit
DVCC3A DVCC3B	Power Supply Voltage	-0.3 to 3.9	V
DVCC1A DVCC1B DVCC1C		-0.3 to 3.0
AVCC		-0.3 to 3.9
VIN	Input Voltage	-0.3 ∼ DVCC3A/3B+0.3 (Note1) -0.3 to AVCC + 0.3 (Note2)	V
IOL	Output Current (1pin)	15	mA
IOH	Output Current (1pin)	-15	mA
IOL	Output Current (total)	80	mA
IOH	Output Current (total)	-50	mA
PD	Power Dissipation (Ta = 85)	600	mW
TSOLDER	Soldering Temperature (10s)	260
TSTG	Storage Temperature	-65 to 150
TOPR	Operation Temperature	-0 to 70
TOPR	Operation Temperature (80MHz)	-0 to 50

Note1: If setting it, don't exceed the Maximum Ratings of DVCC3A (PV port and PW port are DVCC3B).
Note2: In PG0 to PG5, P96,P97,VREFH,VREFL maximum ratings for AVCC is applied.
Note3: The absolute maximum ratings are rated values that must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products that include this device, ensure that no absolute maximum rating value will ever be exceeded.

Description

1) Settings the transfer clock generator and Word Select signal In the I2S unit, the clock frequencies for the I2SnCKO and I2SnWS signals are generated using the system clock (fSYS) as a source clock. The system clock is divided by a prescaler and a dedicated clock generator to set the transfer clock and sampling frequency.
The counters are started by setting I2SnCTL<CNTEn> to "1" and are stopped and cleared by setting <CNTEn> to "0".
A) Clock generator
• 8-bit counter
This is an 8-bit counter that generates the I2SnCKO signal by dividing the clock selected by I2SnCTL<CLKSn>.
• 6-bit counter
This is a 6-bit counter that generates the I2SnWS signal by dividing the I2SnCKO signal.
B) Word Select
• Word Select signal (I2SnWS)
The I2SnWS signal is used to distinguish the position of valid data and whether left data or right data is being transmitted in the I2S format. This signal is clocked out in synchronization with the data transfer clock. In only channel 0, this signal can be used as an AD conversion trigger signal for the ADC. How valid data is to be output in relation to the WS signal can be specified as I2S format, left-justified, or right-justified. In only channel 0, an interrupt request can be output to the ADC on the rising edge of the WS signal. (This is controlled by the ADC's control register.)
(2) Data format
This circuit support I2S format, left justify and right justify format by setting I2SnCTL<DTFMTn1:n0> register. And support stereo and monaural both, controlled by I2SnCTL<FSELn> register.