Features: ` Stereo Audio DAC
102-dBA Signal-to-Noise Ratio
16/20/24/32-Bit Data
Supports Sample Rates From 8 kHz to 96 kHz
3D/Bass/Treble/EQ/De-Emphasis Effects
Flexible Power Saving Modes and Performance are Available
` Stereo Audio ADC
92-dBA Signal-to-Noise Ratio
Supports Sample Rates From 8 kHz to 96 kHz"
Digital Signal Processing and Noise Filtering Available During Record
` Six Audio Input Pins
One Stereo Pair of Single-Ended Inputs
One Stereo Pair of Fully Differential Inputs
` Six Audio Output Drivers
Stereo Fully Differential or Single-Ended Headphone Drivers
Fully Differential Stereo Line Outputs
` Low Power: 14-mW Stereo 48-kHz Playback With 3.3-V Analog Supply
` Ultralow-Power Mode with Passive Analog Bypass
` Programmable Input/Output Analog Gains
` Automatic Gain Control (AGC) for Record
` Programmable Microphone Bias Level
` Programmable PLL for Flexible Clock Generation
` I2C Control Bus
` Audio Serial Data Bus Supports I2S, Left/Right-Justified, DSP, and TDM Modes
` Extensive Modular Power Control
` Power Supplies:
Analog: 2.7 V3.6 V.
Digital Core: 1.525 V1.95 V
Digital I/O: 1.1 V3.6 V
` Package: 5-mm ´ 5-mm 32-Pin QFN
Application· Digital Cameras
· Smart Cellular Phones
· PDAs
· Portable Computing
· Communication
· Entertainment ApplicationsPinout
Specifications
|
VALUE |
UNIT |
| AVDD to AVSS, DRVDD to DRVSS |
0.3 to 3.9 |
V |
| AVDD to DRVSS |
0.3 to 3.9 |
V |
| IOVDD to DVSS |
0.3 to 3.9 |
V |
| DVDD to DVSS |
0.3 to 2.5 |
V |
| AVDD to DRVDD |
0.1 to 0.1 |
V |
| Digital input voltage to DVSS |
0.3 to IOVDD + 0.3 |
V |
| Analog input voltage to AVSS |
0.3 to AVDD + 0.3 |
V |
| Operating temperature range |
40 to 85 |
|
| Storage temperature range |
65 to 105 |
|
| TJ Max Junction temperature |
105 |
|
| Power dissipation |
(TJ Max TA)/RJA |
W |
| RJA Thermal impedance |
44 |
/W |
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) ESD complicance tested to EIA/JESD22-A114-B and passed.
DescriptionThe TLV320AIC3104 is a low-power stereo audio codec with stereo headphone amplifier, as well as multiple inputs and outputs that are programmable in single-ended or fully differential configurations. Extensive register-based power control is included, enabling stereo 48-kHz DAC playback as low as 14 mW from a 3.3-V analog supply, making it ideal fo portable battery-powered audio and telephony applications.
The record path of the TLV320AIC3104 contains integrated microphone bias, digitally controlled stereo microphone preamplifier, and automatic gain control (AGC), with mix/mux capability among the multiple analog inputs. Programmable filters are available during record which can remove audible noise that can occur during optical zooming in digital cameras The playback path includes mix/mux capability from the stereo DAC and selected inputs, through programmable volume controls, to the various outputs.
The TLV320AIC3104 contains four high-power output drivers as well as two fully differential output drivers. The high-power output drivers are capable of driving a variety of load configurations, including up to four channels of single-ended 16- headphones using ac-coupling capacitors, or stereo 16-headphones in a capless output configuration.
The stereo audio DAC supports sampling rates from 8 kHz to 96 kHz and includes programmable digital filtering in the DAC path for 3D, bass, treble, midrange effects, speaker equalization, and de-emphasis for 32-kHz, 44.1-kHz, and 48-kHz sample rates. The stereo audio ADC supports sampling rates from 8 kHz to 96 kHz and is preceded by programmable gain amplifiers or AGC that can provide up to 59.5-dB analog gain for low-level microphone inputs. The TLV320AIC3104 provides an extremely high range of programmability for both attack (81,408 ms) and for decay (0.0522.4 seconds). This extended AGC range allows the AGC to be tuned for many types of applications.
For battery saving applications where neither analog nor digital signal processing are required, the device can be put in a special analog signal passthrough mode. This mode significantly reduces power consumption, as most of the device is powered down during this passthrough operation.
The serial control bus supports the I2C protocol, whereas the serial audio data bus is programmable for I2S, left/right-justified, DSP, or TDM modes. A highly programmable PLL is included for flexible clock generation and support for all standard audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz, with special attention paid to the most-popular cases of 12-MHz, 13-MHz, 16-MHz, 19.2-MHz, and 19.68-MHz system clocks.
The TLV320AIC3104 operates from an analog supply of 2.7 V3.6 V, a digital core supply of 1.525 V1.95 V, and a digital I/O supply of 1.1 V3.6 V. The device is available in a 5-mm * 5-mm 32-pin QFN package.
TLV320AIC3104 Data Sheet
