TLC2578

Features: 14-Bit Resolution for TLC3574/78, 12-Bit for TLC2574/2578Maximum Throughput 200-KSPSMultiple Analog Inputs: 8 Single-Ended Channels for TLC3578/2578 4 Single-Ended Channels for TLC3574/2574Analog Input Range: ±10 VPseudodifferential Analog InputsSPI/DSP-Compatible Serial Interfaces With ...

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TLC2578 Picture
SeekIC No. : 004520483 Detail

TLC2578: Features: 14-Bit Resolution for TLC3574/78, 12-Bit for TLC2574/2578Maximum Throughput 200-KSPSMultiple Analog Inputs: 8 Single-Ended Channels for TLC3578/2578 4 Single-Ended Channels for TLC3574/257...

floor Price/Ceiling Price

Part Number:
TLC2578
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/1/11

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Product Details

Description



Features:

14-Bit Resolution for TLC3574/78, 12-Bit for TLC2574/2578
Maximum Throughput 200-KSPS
Multiple Analog Inputs:
8 Single-Ended Channels for TLC3578/2578
4 Single-Ended Channels for TLC3574/2574
Analog Input Range: ±10 V
Pseudodifferential Analog Inputs
SPI/DSP-Compatible Serial Interfaces With SCLK up to 25-MHz
Built-In Conversion Clock and 8x FIFO
Single 5-V Analog Supply; 3-/5-V Digital Supply
Low-Power
5.8 mA in Normal Operation
20 A in Power Down
Programmable Autochannel Sweep and Repeat
Hardware-Controlled, Programmable Sampling Period
Hardware Default Configuration
INL: TLC3574/78: ±1 LSB;
           TLC2574/78: ±0.5 LSB
DNL: TLC3574/78: ±0.5 LSB;
            TLC2574/78: ±0.5 LSB
SINAD: TLC3574/78: 79 dB;
               TLC2574/78: 72 dB
THD: TLC3574/78: 82 dB;
            TLC2574/78: 82 dB



Pinout

  Connection Diagram


Specifications

Supply voltage, GND to AVDD and DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 6.5 V
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 V to 17 V
Analog input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA MAX
Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to DVDD + 0.3 V
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 150°C
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Lead temperature 1,6 mm (1.16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under electrical characteristics and timing characteristics is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.



Description

The TLC3574, TLC3578, TLC2574, and TLC2578 are a family of high-performance, low-power, CMOS analog-to-digital converters (ADC). TLC3574/78 is a 14-bit ADC; TLC2574/78 is a 12-bit ADC. All parts operate from single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital input [chip select (CS), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS (works as SS, slave select), SDI, SDO and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters connect to one serial port of a DSP, CS works as the chip select to allow the host DSP to access the individual converter. CS can be tied to ground if only one converter is used. FS must be tied to DVDD if it is not used (such as in an SPI interface). When SDI is tied to DVDD, the device is set in hardware default mode after power on and no software configuration is required. In the simplest case, only three wires (SDO, SCLK, and CS or FS) are needed to interface with the host.




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