TL16C752C

` ST16C654/654D Pin Compatible With
` RS-485 Mode Support Additional Enhancements (PFB Package Only)
` Support 1.8-V, 2.5-V, 3.3-V, or 5-V Supply
` Supports up to 24-MHz Crystal Input Clock
` Characterized for Operation From 40 to (1.5 Mbps) 85 , Available in Commercial and Industrial
` Supports up to 48-MHz Oscillator Input Clock Temperature Grades(3 Mbps) for 5-V Operation
` Software-Selectable Baud-Rate Generator
` Supports up to 32-MHz Oscillator Input Clock
` Prescalable Provides Additional Divide-by-4(2 Mbps) for 3.3-V Operation Function
` Supports up to 24-MHz Input Clock (1.5 Mbps)
` Programmable Sleep Mode for 2.5-V Operation
` Programmable Serial Interface Characteristics
` Supports up to 16-MHz Input Clock (1 Mbps) 5-, 6-, 7-, or 8-Bit Characters for 1.8-V Operation
Even, Odd, or No Parity Bit Generation and
` 64-Byte Transmit FIFO Detection
` 64-Byte Receive FIFO With Error Flags 1-, 1.5-, or 2-Stop Bit Generation
` Programmable and Selectable Transmit and
` False Start Bit Detection Receive FIFO Trigger Levels for DMA and Interrupt Generation
` Complete Status Reporting Capabilities in Both Normal and Sleep Mode
` Programmable Receive FIFO Trigger Levels for Software/Hardware Flow Control
` Line Break Generation and Detection
` Software/Hardware Flow Control
` Internal Test and Loopback Capabilities
Programmable Xon/Xoff Characters
` Fully Prioritized Interrupt System Controls
Programmable Auto-RTS and Auto-CTS
` Modem Control Functions (CTS, RTS, DSR,DTR, RI, and CD)
` Optional Data Flow Resume by Xon Any Character
` IrDA Capability
` DMA Signaling Capability for Both Received and Transmitted Data on PN Package

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

The TL16C752C is a quad universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 3 Mbps. It incorporates the functionality of four UARTs, each UART having its own register set and FIFOs. The four UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the UART function is asynchronous communications element (ACE), and these terms are used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that four such devices are incorporated into the TL16C752C. The TL16C752C offers enhanced features. It has a transmission control register (TCR) that stores received FIFO threshold level to start/stop transmission during hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics.

Each UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1-, 1.5-, or 2-stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and software flow control and hardware flow control capabilities.

The TL16C752C is available in a 32-pin QFN (RHB) package. A 48-pin QFP (PFB) package will be available in late 2008.