THS8083

• Analog Channels Three digitizing channels, each with independently controllable clamp, PGA, and ADC. Clamp: 256-step programmable RGB or YUV clamping during external or internal clamp timing window PGA: 6-bit coarse/5-bit fine programmable gain amplifier ADC: 8 bit 80 MSPS (THS8083) or 95 MSPS (THS8083-95) A/D converter  Composite Sync: Integrated sync-on-green/sync-on-luminance extraction Support for ac-coupled input signals
• PLL Fully integrated digital PLL (including loop filter) for pixel clock generation 10-80 MHz (THS8083) or 10-95 MHz (THS8083-95) pixel clock generation from reference input Adjustable PLL loop bandwidth for minimum jitter or fast acquisition/wide capture range modes 5-bit programmable subpixel accuracy positioning of sampling phase Noise gates on HS input to avoid false PLL updating
• Output Formatter Single and double pixel width output data bus for reduced board clock frequency and EMI Support for 4:4:4 and 4:2:2 (ITU.BT601 style) output modes to reduce board traces to video ASICs Dedicated DATACLK1 output for easy latching of output data
• System Industry-standard normal/fast I2C interface with register readback capability Support for input format detection via integrated monitoring of HS, VS, and pixel clock frequencies Support for multidevice operation (master/slave operation for SXGA resolution) Space-saving TQFP-100 pin package Thermally-enhanced PowerPADE package for better heat dissipation
• Applications LCD desktop monitors and LCD or DMD-based projection systems Videoconferencing PCTV set-top boxes, digital TV sets, and multimedia cards Scan rate/image resolution converters Video/graphics digitizing equipment (RGB or YUV-based)