TDAT162G52

* This maximum rating only applies when the device is powered up with VDDD.
† Depending on the application for both the 792 PBGA and 600 LBGA, a heat sink may be required (suggested heat sink assembly for 600-pin LBGA package (ChipCoolers part number HST357-D with airflow of 400 LFPM) or equivalent.

The TDAT162G52 expected concatenation map register is programmed via programmable registers (Table 417) on a per timeslot
(STS-1) basis. The concatenation state of each time slot can be read from the received concatenation map register (RXT_RCNCTM_TSBSR[A-D], Received Concatenation Map Time Slots 1-12 in Bytestream A-D (RO), Table 419). Comparison of the expected and received concatenation state is enabled on a per time-slot basis by software setting of the concatenation compare enable register (RXT_CNCTCPREN_TSBSR[A-D], Concatenation Compare Enable Time Slots 1-12 in Bytestream A-D (R/W, Control), Table 418). Alarms are binned on a   rbytestream (STS-12) basis in the concatenation map mismatch register (RXT_CNCTMM_ALMBNBSR, Channel Path Concatenation Map Mismatch Alarm Status Binning Bytestream A-D (RO, COR/COW), Table 344), and resulting interrupts can be masked by the concatenation map mismatch mask register (see RXT_CNCTMM_ALMMBSR, Channel Path Concatenation Map Mismatch Alarm Status Masks Bytestream A-D
(R/W), Table 376); mismatches in the first time slot of a bytestream are special cases. When the expected state of
a bytestream is concatenation and the received state is normal, the mismatch status bit for the previous bytestream
will be set since the errored time slot is trying to concatenate to an STS-1 in the previous bytestream.