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TDA4691

Features: ` Sync processor for horizontal (H) and vertical (V) sync pulses generated by internal 13.5 MHz oscillator` Stable 'On Screen Display (OSD)', if no input signal is present with free running internal oscillator; automatic turn over to locked oscillator, if input signal is available` Exter...

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SeekIC No. : 004516373 Detail

TDA4691: Features: ` Sync processor for horizontal (H) and vertical (V) sync pulses generated by internal 13.5 MHz oscillator` Stable 'On Screen Display (OSD)', if no input signal is present with free runnin...

TDA4691 Data Sheet

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Part Number:
TDA4691
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

` Sync processor for horizontal (H) and vertical (V) sync pulses generated by internal 13.5 MHz oscillator
` Stable 'On Screen Display (OSD)', if no input signal is present with free running internal oscillator; automatic turn over to locked oscillator, if input signal is available
` External clock oscillator can be used
` Standard 50/60 Hz signals are identified automatically
` Additional outputs for 13.5 MHz, composite sync, 50//60 Hz identification, signal identification (mute), super-sandcastle 12 V
` TTL compatible outputs (H, V, composite sync and 13.5 MHz)
` 3 different time constants for the PHI1 PLL: fast, normal and slow (T1, T2 and T3). Fast and normal time constant are set independent from each other
` Start of H-pulse definable by application
` Digital interference reduction for H and V signals
` Digital noise detector
` Time correction of non-standard H-pulses and equalizing pulses for optimum PLL control.


Pinout

Connection Diagram


Specifications

SYMBOL PARAMETER MIN. MAX. UNIT
VP1 supply voltage 0 9.0 V
IP1 supply current - 40 mA
VP2 supply voltage 0 5.7 V
IP2 supply current - 50 mA
Ptot total power dissipation - 650 mW
Tstg storage temperature -25 +150
Tamb operating ambient temperature 0 +70
VESD ESD-protection on all pins; note 1 300 - V
II/O currents on all pins except supply pins 3, 8, 12 and 19 -10 +10 mA
VI voltage applied to pins 1, 2, 4, 5, 7, 14 and 20 0 VP1 V
VI voltage applied to pins 9, 10, 11 and 13 0 VP2 V
V6 voltage applied to pin 6 0 13.2 V
V15 voltage applied to pin 15 0 5 V
V16 voltage applied to pin 16 0 5 V
V17 voltage applied to pin 17 0 5 V
V18 voltage applied to pin 18 0 5 V
Note to the limiting values
1. Equivalent to discharging a 200 pF capacitor through a 0 series resistor.


Description

The TDA4691 is a bipolar integrated circuit for sync processing in 50/100 and 60/120 Hz TV sets, preferably in conjunction with the programmable deflection controller TDA9150. A line locked 13.5 MHz clock with several dividers and logic circuitry is available generating the horizontal and vertical sync outputs. The device can be assembled in a DIL20 or SO20 package.




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