TC7MPH3125FTG

Features:

• Bidirectional interface between 1.2-V and 1.8-V, 1.2-V and 2.5-V, 1.2-V and 3.3-V, 1.5-V and 2.5-V, 1.5-V and 3.3-
   V, 1.8-V and 2.5-V, 1.8-V and 3.3-V or 2.5-V and 3.3-V buses.
• High-speed operation: tpd = 6.8 ns (max) (V_CCA = 2.5 ± 0.2 V, V_CCB = 3.3 ± 0.3 V)
                                       tpd = 8.9 ns (max) (V_CCA = 1.8 ± 0.15 V, V_CCB = 3.3 ± 0.3 V)
                                       tpd = 10.3 ns (max) (V_CCA = 1.5 ± 0.1 V, V_CCB = 3.3 ± 0.3 V)
                                       tpd = 61 ns (max) (V_CCA = 1.2 ± 0.1 V, V_CCB = 3.3 ± 0.3 V)
                                       tpd = 9.5 ns (max) (V_CCA = 1.8 ± 0.15 V, V_CCB = 2.5 ± 0.2 V)
                                       tpd = 10.8 ns (max) (V_CCA = 1.5 ± 0.15 V, V_CCB = 2.5 ± 0.2 V)
                                       tpd = 60 ns (max) (V_CCA = 1.2 ± 0.15 V, V_CCB = 2.5 ± 0.2 V)
                                       tpd = 58 ns (max) (V_CCA = 1.2 ± 0.1 V, V_CCB = 1.8 ± 0.15 V)
• Output current: I_OH/I_OL = ±12 mA (min) (V_CC = 3.0 V)
                            I_OH/I_OL = ±9mA (min) (V_CC = 2.3 V)
                            I_OH/I_OL = ±3 mA (min) (V_CC = 1.65 V)
                            I_OH/I_OL = ±1mA (min) (V_CC = 1.4 V)
• Latch-up performance: ±300 mA
• ESD performance: Machine model ±200 V 
                                Human body model ±2000 V
• Ultra-small package: VSSOP (US16), VQON16
• Bushold circuit is build in only the B bus side. (Only in OE = "H", a former state is maintained.)
• Low current consumption: Using the new circuit significantly reduces current consumption when OE = "H".
  Suitable for battery-driven applications such as PDAs and cellular phones.
• Floating A-bus and B-bus are permitted. (when OE = "H")
• 3.6-V tolerant function provided on A-bus terminal, DIR and OE terminal.
Note 1: Do not apply a signal to any bus pins when it is in the output mode. Damage may result.
Note:When mounting VQON package, the type of recommended flux is RA or RMA.



Pinout




Specifications

Characteristics	Symbol	Rating	Unit
Power Supply Voltage (Note 2)	VCCA	−0.5 to 4.6	V
	VCCB	−0.5 to 4.6
DC Input Voltage (DIR, OE )	VIN	−0.5 to 4.6	V
DC bus I/O Voltage	VI/OA	−0.5 to 4.6 (Note 3)	V
		−0.5 to VCCA + 0.5 (Note 4)
	VI/OB	−0.5 to VCCB + 0.5 (Note 4)
Input diode Current	IIK	-50	mA
Output diode Current	II/OK	±50 (Note 5)	mA
DC Output Current	IOUTA	±25	mA
	IOUTB	±25
DC VCC/ground current per supply pin	ICCA	±50	mA
	ICCB	±50
Power Dissipation	PD	180	mW
Storage Temperature	TSTG	-65 to +150

Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance 
            or even destruction.

            Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
            significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
            even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
            maximum ratings and the operating ranges.

            Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
            ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e.
            reliability  test report and estimated failure rate, etc).

Note 2: Don't supply a voltage to V_CCB pin when V_CCA is in the OFF state.
Note 3: Output in OFF state
Note 4: High or Low stats. IOUT absolute maximum rating must be observed.
Note 5: V_OUT < GND, V_OUT > V_CC


Description

The TC7MPH3125FK/TC7MPH3125FTG is a dual supply, advanced high-speed CMOS 4-bit dual supply voltage interface bus transceiver fabricated with silicon gate CMOS technology.

Designed for use as an interface between a 1.2-V, 1.5-V, 1.8-V, or 2.5-V bus and a 1.8-V, 2.5-V or 3.6-V bus in mixed 1.2-V, 1.5-V, 1.8-V or 2.5-V/1.8-V, 2.5-V or 3.6-V supply systems.

The A-port interfaces of TC7MPH3125FTG with the 1.2-V, 1.5-V, 1.8-V or 2.5-V bus, the B-port with the 1.8-V, 2.5-V, 3.3-V bus.

The direction of data transmission is determined by the level of the DIR input. The enable input (OE) of TC7MPH3125FTG can be used to disable the device so that the buses are effectively isolated. The bus of a B bus side at floating state is maintained in an appropriate logic level due to a bushold circuit to a B bus. Moreover, the bushold circuit which is added to a B bus is off when OE is low.

All inputs of TC7MPH3125FTG are equipped with protection circuits against static discharge or transient excess voltage.