Features: `High speed: fmax = 140 MHz (typ.) (VCC= 5 V)
`Low power dissipation: ICC = 4A (max) (Ta = 25)
`Compatible with TTL outputs: VIL = 0.8 V (max) VIH = 2.0 V (min)
`Power down protection is provided on all inputs and outputs. Balanced propagation delays: tpLH tpHL
`Low noise: VOLP= 1.5 V (max)
`Pin and function compatible with the 74 series (74AC/HC/F/ALS/LS etc.) 574 type. Pinout
Specifications
|
Characteristics |
Symbol |
Rating
|
Unit |
| Supply voltage range |
VCC |
-0.5~7.0 |
V |
| DC input voltage |
VIN |
-0.5~7.0 |
V |
| DC output voltage |
VOUT |
-0.5~7.0(Note 2) |
V |
|
-0.5~VCC+0.5 (Note 3) |
| Input diode current |
IIK |
-20 |
mA |
| Output diode current |
IOK |
±20 (Note 4) |
mA |
| DC output current |
IOUT |
±25 |
mA |
| DC VCC/ground current |
ICC |
±75 |
mA
|
| Power dissipation |
PD |
180 |
mW |
| Storage temperature |
Tstg |
-65~150 |
|
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc).
Note 2: Output in off-state
Note 3: High or low state. IOUT absolute maximum rating must be observed.
Note 4: VOUT <GND, VOUT >VCC
DescriptionThe TC7MET374AFK is an advanced high speed CMOS octal flip-flop with 3-state output fabricated with silicon gate C2MOS technology.
TC7MET374AFK achieves the high speed operation similar to equivalent bipolar schottky TTL while maintaining the CMOS low power dissipation.
This 8-bit D-type flip-flop is controlled by a clock input (CK) and a output enable input (OE).
When the OE input is high, the eight outputs of TC7MET374AFK are in a high impedance state.
The input voltage are compatible with TTL output voltage. The TC7MET374AFK may be used as a level converter for nterfacing 3.3 V to 5 V system.
Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (Note) pins without regard to the supply voltage. These structure prevents TC7MET374AFK destruction due to mismatched supply and input/output voltages such as battery back up, hot board insertion, etc.
TC7MET374AFK Data Sheet
