TC59LM914/06AMG-37

Features: • Fully Synchronous Operation• Double Data Rate (DDR)Data input/output are synchronized with both edges of DQS.• Differential Clock (CLK and CLK ) inputsCS, FN and all address input signals are sampled on the positive edge of CLK.Output data (DQs and DQS) is aligned to ...

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SeekIC No. : 004514229 Detail

TC59LM914/06AMG-37: Features: • Fully Synchronous Operation• Double Data Rate (DDR)Data input/output are synchronized with both edges of DQS.• Differential Clock (CLK and CLK ) inputsCS, FN and all ad...

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Part Number:
TC59LM914/06AMG-37
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/1/12

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Product Details

Description



Features:

• Fully Synchronous Operation
• Double Data Rate (DDR)
Data input/output are synchronized with both edges of DQS.
• Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and DQS) is aligned to the crossings of CLK andCLK .
• Fast clock cycle time of 3.75 ns minimum
Clock: 266 MHz maximum
Data: 533 Mbps/pin maximum
• Fast cycle and Short Latency
• Eight independent banks operation
When BA2 input assign to A14 input, TC59LM914/06AMG can function as 4 bank device
(Keep backward compatibility to 256Mb)
• Bidirectional differential data strobe signal : TC59LM906AMG
• Bidirectional data strobe signal per byte : TC59LM914AMG
• Distributed Auto-Refresh cycle in 3.9 s
• Self-Refresh
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency-1
• Programable CAS Latency and Burst Length
CAS Latency = 3, 4, 5
Burst Length = 2, 4
• Organization: TC59LM914AMG : 4,194,304 words * 8 banks * 16 bits
TC59LM906AMG : 8,388,608 words * 8 banks * 8 bits
• Power Supply Voltage VDD: 2.5 V ± 0.125V
VDDQ: 1.4 V ∼ 1.9 V
• 1.8 V CMOS I/O comply with SSTL_18 and HSTL
• Package: 60Ball BGA, 1mm * 1mm Ball pitch (P−BGA64−1317−1.00AZ)



Specifications

SYMBOL PARAMETER RATING UNIT NOTES
VDD Power Supply Voltage −0.3~ 3.3 V  
VDDQ Power Supply Voltage (for I/O buffer) −0.3~VDD+ 0.3 V  
VIN Input Voltage −0.3~VDD+ 0.3 V  
VOUT Output and I/O pin Voltage −0.3~VDDQ + 0.3 V  
VREF Input Reference Voltage −0.3~VDD+ 0.3 V  
Topr Operating Temperature (case) 0~85  
Tstg Storage Temperature −55~150  
Tsolde Soldering Temperature (10 s) 260  
PD Power Dissipation 2 W  
IOUT Short Circuit Output Current ±50 mA  

Caution: Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this specification.
Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability




Description

Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM914/06AMG-37 is Fast Cycle Random Access Memory (Network FCRAMTM) containing 536,870,912 memory cells. TC59LM914/06AMG-37 is organized as 4,194,304-words × 8 banks × 16 bits, TC59LM914/06AMG-37 is organized as 8,388,608-words × 8 banks × 8 bits.

TC59LM914/06AMG-37 feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence.

TC59LM914/06AMG-37 can operate fast core cycle compared with regular DDR SDRAM.

TC59LM914/06AMG-37 is suitable for Network, Server and other applications where large memory density and low power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data transfer under light loading condition.




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