TC59LM913AMG-50 Selling Leads, Price trend, TC59LM913AMG-50 DataSheet download, circuit diagram from SeekIC.com

Features: • Fully Synchronous Operation • Double Data Rate (DDR) Data input/output are synchronized with both edges of DQS.• Differential Clock (CLK and CLK ) inputs CS, FN and all address input signals are sampled on the positive edge of CLK. Output data (DQs and DQS) is aligne...

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SeekIC No. : 004514228 Detail

TC59LM913AMG-50: Features: • Fully Synchronous Operation • Double Data Rate (DDR) Data input/output are synchronized with both edges of DQS.• Differential Clock (CLK and CLK ) inputs CS, FN and all...

TC59LM913AMG-50 Data Sheet

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Part Number:: TC59LM913AMG-50
Supply Ability:: 5000

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15 Days

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Product Details

Description

Features:

• Fully Synchronous Operation
• Double Data Rate (DDR) Data input/output are synchronized with both edges of DQS.
  • Differential Clock (CLK and CLK ) inputs CS , FN and all address input signals are sampled on the positive
     edge of CLK. Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .
• Fast clock cycle time of 5 ns minimum
   Clock: 200 MHz maximum
   Data: 400 Mbps/pin maximum
• Fast cycle and Short Latency
• Eight independent banks operation When BA2 input assign to A14 input, TC59LM913AMG can function as
4bank device (Keep backward compatibility to 256Mb)
• Bidirectional Data Strobe Signal
• Distributed Auto-Refresh cycle in 3.9 µs
• Self-Refresh
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency-1
• Programable CAS Latency and Burst Length
   CAS Latency = 4
   Burst Length = 2, 4
• Organization: TC59LM913AMG : 4,194,304 words × 8 banks × 16 bits
• Power Supply Voltage V_DD: 2.5 V ± 0.15V
                                      V_DDQ: 2.5 V ± 0.15 V
• 2.5 V CMOS I/O comply with SSTL_2 (half strength driver)
• Package: 60Ball BGA, 1mm × 1mm Ball pitch (P−BGA64−1317−1.00AZ)
• Lead-Free
• Keep backward compatibility for TC59LM814CFT(256Mbits) except package design.
   Notice : FCRAM is trademark of Fujitsu Limited, Japan.

Specifications

SYMBOL	PARAMETER	RATING	UNIT	NOTES
V_DD	Power Supply Voltage	−0.3~3.3	V
V_DDQ	Power Supply Voltage (for I/O buffer)	−0.3~V_DD+ 0.3	V
V_IN	Input Voltage	−0.3~V_DD+ 0.3	V
V_OUT	Output and I/O pin Voltage	−0.3~V_DDQ + 0.3	V
V_REF	Input Reference Voltage	−0.3~V_DD+ 0.3	V
T_CASE	Operating Temperature (case)	0~85
T_stg	Storage Temperature	−55~150
T_solder	Soldering Temperature (10 s)	260
P_D	Power Dissipation	2	W
I_OUT	Short Circuit Output Current	±50	mA

Caution: Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent
              damage to the device. The device is not meant to be operated under conditions outside the
               limits described in the operational section of this Exposure to "ABSOLUTE MAXIMUM RATINGS
               "conditions for extended periods may affect device reliability. specification.

Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability.

Description

Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM913AMG-50 is Network FCRAMTM containing 536,870,912 memory cells. TC59LM913AMG-50 is organized as 4,194,304-words × 8 banks × 16 bits. TC59LM913AMG-50 feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence.

TC59LM913AMG-50 can operate fast core cycle compared with regular DDR SDRAM.

TC59LM913AMG-50 is suitable for Network, Server and other applications where large memory density and low power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data transfer under light loading condition.

TC59LM913AMG-50

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