Features:
|
PARAMETER |
TC59LM913AMB-50 |
| tCK Clock Cycle Time (min) |
CL = 4 |
5.0 ns |
| tRC Random Read/Write Cycle Time (min) |
25.0 ns |
| tRAC Random Access Time (max) |
22.0 ns |
| IDD1S Operating Current (single bank) (max) |
240 mA |
| lDD2P Power Down Current (max) |
80 mA |
| lDD6 Self-Refresh Current (max) |
20 mA |
• Fully Synchronous Operation
• Double Data Rate (DDR)
Data input/output are synchronized with both edges of DQS.
• Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .
• Fast clock cycle time of 5 ns minimum
Clock: 200 MHz maximum
Data: 400 Mbps/pin maximum
• Fast cycle and Short Latency
• Eight independent banks operation
When BA2 input assign to A14 input, TC59LM913AMB can function as 4bank device (Keep backward compatibility to 256Mb)
• Bidirectional Data Strobe Signal
• Distributed Auto-Refresh cycle in 3.9 s
• Self-Refresh
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency-1
• Programable CAS Latency and Burst Length
CAS Latency = 4
Burst Length = 2, 4
• Organization: TC59LM913AMB : 4,194,304 words * 8 banks * 16 bits
• Power Supply Voltage VDD: 2.5 V ± 0.15V VDDQ: 2.5 V ± 0.15 V
• 2.5 V CMOS I/O comply with SSTL_2 (half strength driver)
• Package: 60Ball BGA, 1mm * 1mm Ball pitch (P−BGA64−1317−1.00AZ)
• Keep backward compatibility for TC59LM814CFT(256Mbits) except package design.
Notice : FCRAM is trademark of Fujitsu Limited, Japan.
Specifications
|
SYMBOL |
PARAMETER |
RATING |
UNIT |
|
VDD |
Power Supply Voltage |
−0.3~3.3 |
V |
|
VDDQ |
Power Supply Voltage (for I/O buffer) |
−0.3~VDD+ 0.3 |
V |
|
VIN |
Input Voltage |
−0.3~VDD+ 0.3 |
V |
|
VOUT |
Output and I/O pin Voltage |
−0.3~VDDQ + 0.3 |
V |
|
VREF |
Input Reference Voltage |
−0.3~VDD+ 0.3 |
V |
|
TCASE |
Operating Temperature (case) |
0~85 |
|
|
Tstg |
Storage Temperature |
−55~150 |
|
|
Tsolder |
Soldering Temperature (10 s) |
260 |
|
|
PD |
Power Dissipation |
2 |
W |
|
IOUT |
Short Circuit Output Current |
±50 |
mA |
Caution: Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device.The device is not meant to be operated under conditions outside the limits described in the operational section of this specification.
Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability.
DescriptionNetwork FCRAMTM TC59LM913AMB-50 is Double Data Rate Fast Cycle Random Access Memory. TC59LM913AMB-50 is Network FCRAMTM containing 536,870,912 memory cells. TC59LM913AMB-50 is organized as 4,194,304-words × 8 banks × 16 bits. TC59LM913AMB feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence.TC59LM913AMB-50 can operate fast core cycle compared with regular DDR SDRAM.
TC59LM913AMB-50 is suitable for Network, Server and other applications where large memory density and low power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data transfer under light loading condition.
TC59LM913AMB-50 Data Sheet
