TC4015BFN

PinoutSpecifications Characteristics Symbol Rating Unit DC supply voltage VDD VSS − 0.5~VSS + 20 V Input voltage VIN VSS − 0.5~VDD + 0.5 V Output voltage VOUT VSS − 0.5~VDD + 0.5 V DC input current IIN ±10 mA Powe...

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SeekIC No. : 004513627 Detail

TC4015BFN: PinoutSpecifications Characteristics Symbol Rating Unit DC supply voltage VDD VSS − 0.5~VSS + 20 V Input voltage VIN VSS − 0.5~VDD + 0.5 V Outp...

floor Price/Ceiling Price

Part Number:
TC4015BFN
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/1/12

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Product Details

Description



Pinout

  Connection Diagram


Specifications

Characteristics
Symbol
Rating
Unit
DC supply voltage
VDD
VSS − 0.5~VSS + 20
V
Input voltage
VIN
VSS − 0.5~VDD + 0.5
V
Output voltage
VOUT
VSS − 0.5~VDD + 0.5
V
DC input current
IIN
±10
mA
Power Dissipation
PD
300 (DIP)/180 (SOIC)
mW
Operating temperature range
Topr
−40~85
Storage Temperature range
TSTG
−65~150
Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
         even destruction.

         Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
         significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
         even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
         maximum ratings and the operating ranges.

        Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
        ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability
        test report and estimated failure rate, etc).




Description

TC4015BFN contains two circuits of 4 stage shift registers and the independent output is drived from each stage. As all the D type flip-flops of every stage have common RESET input, asynchronous clear operation can be achieved by an external signal at arbitrary timing. The flip-flop of each stage is triggered by rising edge of CLOCK input.

RESET input of "H" level resets the contents of all the stages to "L" regardless of CLOCK and DATA inputs and all of data outputs Q1 through Q4 become "L".

This can be used for converting serial data to palallel one and for ring counters of any numbering systems.




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