TC11L003

The TC11L003 belongs to TC11L family. These two gate array families provide a unique solution for designs which have a high ratio of pin count to gates. Toshiba's optimized assembly technology allows the use of smaller die sizes in traditional plastic and ceramic flat packsethus providing a silicon efficient solution for pad limited designs. Applications include any low gate county high pin count design (for example, peripheral interfaces and 32- and 64-bit bus applications).

The features of TC11L003 can be summarized as (1)The toshiba design environment embraces popular EWS and CAE systems such as: AIDA, Cadence, Dazix, HILO, HP, IKOS, Mentor, Synopsys, Valid, Verilog-XL and Viewlogic; (2)comprehensive cell libraries with helpful utilities for all product families; (3)logic synthesis capability supported through synopsis; (4)design interface thru hardware description language; (5)design for test features include support for SCAN: AIDA, JTAG, Toshiba scan bureau service; (6)design assistance through local design centers which are supported by U.S. headquarters in sunnyvale, CA; (7)flexibility in design services and interface TC11L, 1.5m CMOS; (8)300, 500 and 700 usable gates; (9)0.6ns typical delay; (10)44 pads; (11)through hole and surface mount packaging - 16 to 42 pin DIP - 24, 28 SOP - 44 PLCC - -44 QFP; (12)compatible with the TC110G "parent family" - process technology - internal gate delays - tested, verified cell libraries; (13)TC14L, 1.0m CMOS; (14)1K, 2K, 4K, 5K, 6K, 7K, 8K,10K usable gates; (15)0.4ns typical delay; (16)from 100 to 208 pads; (17)through hole and surface mount packaging - 84 PLCC - 120, 144, 160, 178, 184, 208 QFP - 80, 100 RFP; (18)compatible with the TC140G "parent family" - process technology - internal gate delays - tested, verified cell libraries.

The absolute maximum ratings of TC11L003 are (1)VDD DC supply voltage: -0.3 to +7.0V; (2)VIN DC input voltage: -0.3 to VDD+0.3V; (3)IIN DC input current: ±10mA; (4)Tstg storage temperature: -40 to +125°C.