T89C51CC01

• 80C51 Core Architecture
• 256 Bytes of On-chip RAM
• 1K Bytes of On-chip ERAM
• 32K Bytes of On-chip Flash Memory Data Retention: 10 Years at 85°CRead/Write Cycle: 10K
• 2K Bytes of On-chip Flash for Bootloader
• 2K Bytes of On-chip EEPROMRead/Write Cycle: 100K
• 14-sources 4-level Interrupts
• Three 16-bit Timers/Counters
• Full Duplex UART Compatible 80C51
• Maximum Crystal Frequency 40 MHz InX2Mode,20MHz(CPUCore,40MHz)
• Five Ports: 32 + 2 Digital I/O Lines
• Five-channel 16-bit PCA with: PWM (8-bit) High-speed Output Timer and Edge Capture
• Double Data Pointer
• 21-bit WatchDog Timer (7 Programmable Bits)
• A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs
• Full CAN Controller: Fully Compliant with CAN Rev2.0A and 2.0B Optimized Structure for Communication Management (Via SFR) 15 Independent Message Objects: Each Message Object Programmable on Transmission or Reception Individual Tag and Mask Filters up to 29-bit Identifier/Channel 8-byte Cyclic Data Register (FIFO)/Message Object 16-bit Status and Control Register/Message Object 16-bit Time-Stamping Register/Message Object CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each MessageObject Access to Message Object Control and Data Registers Via SFR Programmable Reception Buffer Length Up To 15 Message Objects Priority Management of Reception of Hits on Several MessageObjects at theSame Time (Basic CAN Feature) Priority Management for Transmission Message Object Overrun Interrupt Supports: Time Triggered Communication Autobaud and Listening Mode Programmable Automatic Reply Mode 1-Mbit/s Maximum Transfer Rate at 8 MHz (1)Crystal Frequency in X2 Mode Readable Error Counters Programmable Link to On-chip Timer for Time Stamping and NetworkSynchronization Independent Baud Rate Prescaler Data, Remote, Error and Overload Frame Handling
• On-chip Emulation Logic (Enhanced Hook System)
• Power Saving Modes: Idle Mode Power-down Mode

The T89C51CC01 is the first member of the CANaryTM family of 8-bit microcontrollersdedicated to CAN network applications.

In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.Besides the full CAN controller T89C51CC01 provides 32K Bytes of Flash memoryincluding In-System-Programming (ISP), 2K Bytes Boot Flash Memory, 2K BytesEEPROM and 1.2-Kbyte RAM.

Primary attention is paid to the reduction of the electro-magnetic emission ofT89C51CC01.